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A 1.2-V 72-Mb double data rate 3 (DDR3) SRAM achieves a data rate of 1.5 Gb/s using dynamic self-resetting circuits. Single-ended main data lines halve the data line precharging power dissipation and the number of data lines. Clocks phase shifted by 0°, 90°, and 270° are generated through the proposed clock adjustment circuits. The latter circuits...
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A Physical unclonable function (PUF), alike a fingerprint, exploits manufacturing randomness to endow each physical item with a unique identifier. One primary PUF application is the secure derivation of volatile cryptographic keys using a fuzzy extractor comprising of: i) a secure sketch; and ii) an entropy extractor. Although the entropy extractor...
Citations
... The BS needs to provide the computation result of the l-th service if and only if |K l | ≥ 1, ∀s l ∈ S. We adopt a commonly used computation model [13], in which the total number of 1 The delay of proactive offloading and executing the input data is sufficiently small compared with the deadline, and therefore the computation results can be reused for a long period of time in the future. 2 We assume a type of on-chip caching facilities that incurs negligible accessing delay, e.g., SRAM, with reading/writing speed of 1.5Gb/s and S around 72Mbits [25]. CPU cycles required for performing one computation task is linearly proportioned to its task input bit length. ...
With the growing demand for latency-critical and computation-intensive Internet of Things (IoT) services, mobile edge computing (MEC) has emerged as a promising technique to reinforce the computation capability of the resource-constrained mobile devices. To exploit the cloud-like functions at the network edge, service caching has been implemented to (partially) reuse the computation tasks, thus effectively reducing the delay incurred by data retransmissions and/or the computation burden due to repeated execution of the same task. In a multiuser cache-assisted MEC system, designs for service caching depend on users' preference for different types of services, which is at times highly correlated to the locations where the requests are made. In this paper, we exploit users' location-dependent service preference profiles to formulate a cache placement optimization problem in a multiuser MEC system. Specifically, we consider multiple representative locations, where users at the same location share the same preference profile for a given set of services. In a frequency-division multiple access (FDMA) setup, we jointly optimize the binary cache placement, edge computation resources and bandwidth allocation to minimize the expected weighted-sum energy of the edge server and the users with respect to the users' preference profile, subject to the bandwidth and the computation limitations, and the latency constraints. To effectively solve the mixed-integer non-convex problem, we propose a deep learning based offline cache placement scheme using a novel stochastic quantization based discrete-action generation method. In special cases, we also attain suboptimal caching decisions with low complexity leveraging the structure of the optimal solution. The simulations verify the performance of the proposed scheme and the effectiveness of service caching in general.
... A programmable impedance controller (PIC) creates the impedance codes, having as reference the external resistors R T and R Q for ODT and OCD, respectively. In [11] a 1.2-V 1.5-Gb/s 72-Mb DDR3 SRAM is described, which satisfies the need for high data rate and area density required in recent ultra fast systems together with the corresponding on-chip termination. In [12] the implementation of a third-generation 1.1-GHz 64-bit microprocessor is presented whereas it provides some details on the DDR1 SSTL I/O circuit solutions at the memory interface. ...
A 1 GHz Double Data Rate 2/3 (DRR2/3) combo Stub Series Terminated Logic (SSTL) driver has been developed for the first time to our knowledge using a 90 nm CMOS process. To satisfy the signal integrity requirements the driver strength is dynamically calibrated and the input/output port is efficiently terminated by on-die resistors. Furthermore, the slew-rate can be sufficiently controlled by selecting an appropriate external resistor. The proposed driver design provides all the required output and termination impedances specified by both the DDR2 and DDR3 standards and occupies a small die area of 0.032 mm2 (differential). Experimental results demonstrate its robustness over process, voltage, and temperature variations.
A Clock-shared differential signaling(CSDS) transmitter is fabricated in 0.13 μm CMOS for 120 Hz 10-bit Full HD TVs. The proposed Tx driver takes advantages of PVT-insensitive tunable termination resistance with double feedback loops, and small reference voltage fluctuation. Moreover, a fully-digital duty cycle corrector is proposed, and compared to non-clock spreading, the relative near-field EMI level of multi-phase clock spreading is enhanced by 4.4 dB at the operating frequency of 500 MHz. The CSDS Tx with 34 channels consumes 300 mW at a 2.5 V power supply and 1.0 Gb/s/ch.
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A 72Mb 6T SRAM is designed with 2times144 separate-I/O and random R/W in parallel per cycle running at 875MHz DDR to achieve 504Gb/s bandwidth. It is fabricated in a 90nm CMOS process. Dual R/W self-timed clocks with core emulators are multiplexed to operate the SRAM core at 875MHz. On-chip DLL, programmable I/O skews, and programmable input termination and output driver impedance with precise linearity are essential for this 504Gb/s interface
A versatile I/O buffer is proposed to interface DDR/DDR2/GDDR3 memory types. A new robust impedance calibration scheme which fills the role of off-chip driver (OCD) and on-die terminator (ODT) for improving signal integrity is introduced. The proposed calibration scheme minimizes quantization error and maintains 30~300Omega impedance within 3% variations
A novel differential pulse-width control loop circuit based on high speed frequency-to-voltage converters is proposed. To demonstrate its functionality, a circuit has been designed and simulated in 0.18mm CMOS technology. Results show that the proposed circuit can correct a clock signal's duty cycle even for frequencies as high as 5 GHz. This design can be used to correct clock signal distortion due to process variations in high speed applications such as half-rate clock and data recovery systems.
Effective design of cache SRAM has always been the challenging task in embedded systems dedicated to image processing applications such as vector quantizer (VQ). The low power high speed SRAM array is the need of VQ. The mathematical model and simulation results for low power, high speed, fault tolerant codebook SRAM is presented in this paper. The cell, precharge, transmission logic, sense amplifier, redundant bits and IOs are modeled and SPICE simulated. Since the codebook has rhythmic nature, the successive multiple read cycles are important than write. The implementation is done at 0.25 mum technology. The results show that the least precharge is at 300 mV. The array operates minimum at 600 mV. The dissipation of 256 b array is 1.8 mW at read speed of 5 Gbits/sec at precharge of 1.25 V and supply of 2.5 V.
