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This paper reviews the technology of high-performance electrical
signaling, presents the current state of the art, and projects future
directions. We have demonstrated equalized electrical signaling between
CMOS integrated circuits at data rates of 4Gb/s. As the factors that
determine this signaling rate all scale with improving technology we
expec...
Contexts in source publication
Context 1
... experimenting with several alternatives, we arrived at the input-multiplexed transmitter architecture using analog equalization to achieve our size and power goals. A block diagram of this transmitter is shown in Fig- ure 8. Equalization is performed by a two-tap analog filter that is realized by having the main transmitter and an equalizing duplicate transmitter sum their output currents on the line. ...
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... analog FIR filters can be constructed by building additional dupli- cates each delayed one bit from the previous duplicate. The input-multiplexed transmitter of Figure 8 is consid- erably smaller than the output-multiplexed transmitter of Figure 7. While layout of the new transmitter is not yet complete, we estimate that it will fit in an area of 0.1mm × 0.1mm, about 2% of the area of the old transmitter. ...
Citations
... In reality, the digital transmission line cannot be considered as lossless. The design rules of thumb [8][9] ...
In this paper, we have proposed a framework of systems-on-chips clustering in application to complicated sensor networks. The framework can be applied to address the communication issues in distributed and large-scaled sensor nodes in wireless sensor network application. There are two communication categories under consideration, i.e. intra-nodes and inter-nodes. Due to the potentially higher frequency in the signal propagation within the sensor node, the characteristics of the interconnect among various systems-on-chips cannot be described in the traditionally lumped R, L, C components. We adapt a distributed transmission line model to address such issues and possibly improve the reliability in the intra-nodes communication. Furthermore, based on the bandwidth requirements of each sensor node, the large-scaled senor network is proposed to be transformed into a maze diagram by a user defined threshold bandwidth, so that many existing approaches may be applied to determine the routing paths in the inter-nodes communication to improve the efficiency of the overall network.
... Currently, popular approaches in high performance transmission include signaling with the incident wave from the transmitter rather than ringing up the line [2][3][4]. To achieve incident-wave signaling, the high speed I/O circuits drive a point-to-point interconnect over a terminated transmission line while the receiver termination absorbs the incident wave preventing any reflection [4]. ...
... Currently, popular approaches in high performance transmission include signaling with the incident wave from the transmitter rather than ringing up the line [2][3][4]. To achieve incident-wave signaling, the high speed I/O circuits drive a point-to-point interconnect over a terminated transmission line while the receiver termination absorbs the incident wave preventing any reflection [4]. To assure signal quality which is prone to deteriorate by process conditions, differential signaling is often used to reject common mode noise, to minimize electro magnetic interference (EMI), and to double the slew rate [3]. ...
The design and implementation of a low power high speed differential signaling input/output (I/O) interface in 0.18 μm CMOS technology is presented. The motivations for smaller signal swings in transmission are discussed. The prototype chip supports 4 Gbps data rate with less than 10 mA current at 1.8 V supply according to Cadence Spectre post-layout simulations. Performance comparisons between the proposed device and other signaling technologies reported recently are given.
... Recent developments in high-speed electrical signaling [10] and parallel optical links [12] enable very high performance interconnection networks. These new technologies also change the design space of interconnection networks and greatly change the cost/performance equation. ...
In applications such as processor-memory interconnect, I/O networks, and router switch fabrics, an interconnection network must be scalable to thousands of high-bandwidth terminals while at the same time being economical in small configurations and robust in the presence of single-point faults. Emerging optical technology enables new topologies by allowing links to cover large distances but at a significant premium in cost compared to high-speed electrical links. Existing topologies do not cost-effectively exploit these optical links. In this paper we introduce SOENet, a family of topologies that exploits emerging high-speed optical and electrical links to provide cost effective scalability, and graceful degradation in the presence of faults. We show that SOENet scales more economically than alternative topologies. For networks scalable to 32,000 nodes, a 32-node SOENet costs 4x less than a 3-D torus. Finally we investigate the fault tolerance properties of these networks and show that they degrade more gracefully in the presence of faults than alternative topologies.
... It is common today to find a 1 GHz processor connected to memory through a 133MHz back-side bus. Even though active research aims to improve pin bandwidth by substantially increasing the pin transfer rates into the Gigabit per second regime [9, 11, 26] , the disparity between the computation capacity and off-chip bandwidth will persist for the foreseeable future. For our experiments , we scale the chip pin density according to the SIA projections for signal pin density at a fixed 400 C Q C X E die size. ...
We study the space of chip multiprocessor (CMP) organizations. We compare the area and performance trade-offs for CMP implementations to determine how many processing cores future server CMPs should have, whether the cores should have in-order or out-of-order issues, and how big the per-processor on-chip caches should be. We find that, contrary to some conventional wisdom, out-of-order processing cores will maximize job throughput on future CMPs. As technology shrinks, limited off-chip bandwidth will begin to curtail the number of cores that can be effective on a single die. Current projections show that the transistor/signal pin ratio will increase by a factor of 45 between 180 and 35 nanometer technologies. That disparity will force increases in per-processor cache capacities as technology shrinks, from 128KB at 100nm, to 256KB at 70nm, and to 1MB at 50 and 35nm, reducing the number of cores that would otherwise be possible
... This section discusses the physical origins of the limitations of conventional electrical interconnects and reviews how the interconnect problem might be addressed electronically, before going on in the next section to look at how optical interconnects can overcome some of these limitations. The issues in the design of high-performance electronic signalling systems are reviewed in [13] and an extensive bibliography of this field is available in references [14] and [15]. ...
... The pitch is set by crosstalk requirements rather than fabrication constraints. Assuming that current flows uniformly within one skin depth of each surface in the stripline and in an equal area in the return path through the ground plane, the maximum bit-rate per line is: where σ = 5.80 × 10 7 Ω -1 m -1 is the conductivity of copper, Z 0 is the characteristic impedance of the line (which is a function of w / h), α is the maximum tolerable loss in dB at a frequency B MAX / 2 (taken to be 2 dB [13]) and µ 0 is the permeability of free space. This gives a data rate limited to 2 Gbit/s by frequency dependent loss due to the skin effect alone. ...
... Laboratory implementations have demonstrated that 10 dB of loss can be equalised in a 4 Gbit/s link, which increases the bandwidth limit by a factor of 25. The power consumption in current technology is around 100 mW per transceiver [13]. ...
...................................................................................................................................... viii List of publications .......................................................................................................................ix Chapter 1: Introduction..................................................................................................................1 1.1 Scope and overall research contribution..............................................................................1 1.2 Motivation............................................................................................................................2 1.2.1 The interconnect problem .............................................................................................2 1.2.2 Capabilities and limitations of electrical interconnects................................................4 1.2.3 Advantages of optical interconnects ......................................
... A signaling technique involves in encoding information into current or voltage, generating a reference against which this quantity is measured, providing terminations to couple signal energy into the transmission medium and absorb energy to prevent unwanted reflections, and controlling signal transitions to limit the spectrum of transmitted energy [1]. An efficient signaling scheme is the one that maximizes the data rate per pin, minimizes power dissipation, and provides good noise immunity [5]. Such signaling convention can dramatically increase available data rate and hence system performance. ...
Abstract The gate length of a few tens of a nanometer,for CMOS has become,a distinct possibility due to technology scaling. Furthermore, the amount of transistors in a single die is increasing steadily over time towards gigascale in- tegration (GSI) level. This development,creates a noise and power dissipation problems into a system design. In addition to this, signaling over nanometer interconnects represents a major bottleneck in ULSI systems due to the dom- inant limitation of signal propagation delays. To a large extent, the on-chip signaling technique determines the reliability, speed, and power consump- tion of a network-on-chip (NoC). An efficient on-chip signaling scheme,is the one that maximizes the data rate per pin, minimizes power dissipation, and provides good noise immunity.,Such signaling convention,can dramatically increase available data rate and hence system,performance. Three signaling techniques, namely voltage- and current-mode differen- tial signaling and simultaneous current-mode bidirectional signaling, were selected from the on-chip signaling scheme, which has a promising feature for the future technology scaling impact,as a case study. Interconnects were modeled,using transmission,line model from Spectre and lumped RC-model. For the latter, the length of the interconnect varied from 0.1 mm to 3 mm. Finally, a 32-bit bus was constructed by utilizing the above mention tech-
The exponential growth of the Internet is driving a demand for routers that operate at increasing bit-rates (OC48 to OC192 to OC768) and that have a very large number of ports (10s to 100s to 1000s). To meet this growing demand, routers are needed that can scale with the demand along both the bit-rate and port-count axes. To scale a router to handle a large number of high-speed ports requires a switching fabric that is itself economically scalable and that provides the quality of service demanded by latency- sensitive traffic. A switching fabric that transports packets from input ports to output ports is at the core of any router. Historically, routers have used switching fabrics based on backplane buses and crossbar switches. Buses, however, are not scalable to high bit rates, and crossbars, because their cost grows as the square of the number of nodes, cannot be economically scaled to large numbers of nodes. A direct interconnection network, like the 3-D torus network used in the Avici TSR, provides a high-performance switching fabric that is economically scalable with a cost that increases linearly with the number of nodes. Torus fabrics can be incrementally expanded or upgraded one node at a time. These networks have high path diversity that enables them to route arbitrary traffic patterns without performance degradation. Moreover, they can be realized with uniformly short fabric channels, reducing cost and enabling the use of modern high-speed signaling technology. Direct interconnection networks have been used for more than a decade in high- performance supercomputers manufactured by Cray Research and others. This high-end computing experience has proven the scalability, economy, and robustness of the technology. Parallel computer networks, by themselves, however, do not provide the
Optical interconnection networks is a promising design alternative for future parallel computer systems. Numerous configurations with different degrees of optics, optoelectronics, and electronics have been proposed. In this paper, some of these interconnection networks and technologies are briefly surveyed. Also, a discussion of their suitability in radar signal processing systems is provided, where several different ways of coarse algorithm mapping are considered. M. Jonsson, "Optical interconnections in parallel radar signal processing systems," Research Report CCA -9909, Centre for Computer Systems Architecture (CCA), Halmstad University, Sweden, Apr. 1999.
This paper develops a novel high-speed inter-chip serial signaling scheme with leakage shunt resistors and termination resistors between the signal trace and the ground. For given abstract topology transmission line based on the data for IBM high-end AS/400 system[1] [2], we put termination resistors at the end of receiver and adjust the shunt and termination resistors value to get the optimal distortion-less transmission line. Analytical formulas are derived to predict the worst case jitter and eye-opening based on bitonic step Response Assumption[3]. Our schemes and the other two comparison cases are discussed.
We present a novel scheme to implement distortionless transmission lines for on-chip electrical signaling. By introducing intentional leakage conductance between the wires of a differential pair, the distortionless transmission line eliminates dispersion caused by the resistive nature of on-chip wires and achieves speed of light transmission. We show that it is feasible to construct distortionless transmission line with conventional silicon process. Simulation results show that using 65nm technology, the proposed scheme can achieve 15Gbits/s bandwidth over a 20mm on-chip serial link without any equalization. This approach offers a six times improvement in delay and 85% reduction in power consumption over a conventional RC wire with repeated buffers.
