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This paper shows that multirate processing in a cascaded discrete-time ΔΣ modulator allows to reduce the power consumption by up to 35%. Multirate processing is possible in a discrete-time ΔΣ modulator by its adaptibility with the sampling frequency. The power reduction can be achieved by relaxing the sampling speed of the first stage and increasin...
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... 1.5-bit quantizer needs to perform a three-level quantiza- tion of the input. It consists of two identical blocks, comprising a comparator preceded by a switched-capacitor (SC) network [ Fig. 5(a)]. This SC network generates two voltage thresholds at a level of and by shifting the positive or the negative input signal by depending on the threshold. The used sampling capacitor is 200 fF. The 1.5-bit output data, is extracted by subtracting both ...
Context 2
... comparator [ Fig. 5(b), left] is based on a regenerative latch driving a Set-Reset (SR) latch [ Fig. 5(b), right]. ...
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Citations
... MASH modulators require accurate gain coefficients and high-gain op-amps to delete the first-stage quantization noise [11][12]. The most advanced CMOS technologies enable high-performance op-amps; however, there is the problem of the high-gain requirement. ...
A discrete-time (DT) high-resolution and low-power sturdy multi-stage noise-shaping (SMASH) sigma-delta (ΣΔ) modulator is introduced. It proposes major solution for high-resolution applications relying on M-bit digital input-feedforward (DFF) technique which eliminates a power-hungry analog adder before the stage's quantizer, decreases number of comparators for quantizer implementation and reduces the swing of the integrator's output and a 2 nd-order noise-coupling (NC) technique realized by few extra analog paths and enhances the noise shaping of the modulator without adding active blocks. The effectiveness of the introduced modulator is supported by the behavioral simulation and extensive mathematical analyses. The proposed modulator along with conventional one is simulated in a 0.18μm CMOS technology. The results indicate an outstanding improvement in dynamic range (DR) and resolution with less complexity.
... Figure 13 shows that the various specification parameters obtained for 12-bit Delta-sigma ADC. Table 1 shows performance comparision of proposed delta-sigma ADC with prior works [39][40][41][42][43][44]. The power of 12-bit incremental delta-sigma ADC is reduced up to 65% when compared with conventional ADCs [45][46][47]. ...
... In the MASH structure, each additional stage leads to an additional quantizer and active elements (OPAMP) and therefore increases the power dissipation. Previous research has introduced several techniques to save the power dissipation in MASH, such as OPAMP sharing [45], multirate VCO-based modulator [46], multirate OPAMP sharing [47,48] and dual-slope quantizer [49]. Most of these works used OPAMP-sharing technique to reduce the required active elements by one, and they also have the additional power dissipation by the quantizer of the further stage. ...
... Wireless communications such as GSM [1], WLAN [2] and WCDMA [3], biomedical sensors [4], seismic monitoring systems [5], and digital audio [6,7] are few examples of growing application fronts which require highprecision data conversion with accuracy ranging between 14 and 24 bits [8]. Sigma-delta (RD) modulators combine the idea of oversampling technique with noise shaping to achieve high levels of conversion accuracy [9]. ...
A new technique to evaluate the quantization error of cascaded sigma-delta modulators in digital domain is presented. It avoids the complications associated with analog extraction of the quantization error in multistage noise shaping (MASH) modulators before feeding the error to the proceeding stage. Instead, the quantization error is estimated and cancelled out by adding a digital subtractor and by injecting a purely analog signal from the preceding stage to the next stage. In comparison to conventional MASH modulator structure, analog circuit requirements of the modulator are therefore relaxed, and the number of switched-capacitor digital-to-analog converters and the associated switching energy are lowered. In the absence of extra switching blocks, less flicker and thermal noise would be also injected into the circuit. Different implementations of MASH modulator are presented and analyzed based on the proposed digital quantization error extraction technique. Behavioral-level simulation results prove the mathematical equivalence of the proposed structures with successful MASH designs found in the literature, and confirm the effectiveness of the idea. For a − 1.4 dB, 19.8 kHz input and an oversampling ratio of 16, a modified 1-V 20-MS/s 2 + 2 MASH modulator achieves a signal-to-noise-and-distortion ratio (SNDR) of 78 dB, when the input of the first quantizer is fed to the second stage. The second design based on digital extraction of quantization error achieves a 71 dB SNDR for a − 8.0 dB, 19.8 kHz input, when the second stage is fed by the output of the first integrator.
... Traditionally, high-performance Analog-to-Digital converters (ADCs) have heavily relied on conventional analog building blocks such as operational amplifiers, transconductors and comparators [8][9][10][11][12][13][14]. ...
... II. SYSTEM OVERVIEW Sigma Delta modulators are high precision systems which find applications in several areas, such as telecommunications [5], signal processing [6], [7], and biomedical engineering applications [8]. Such a circuit converts an analog input signal U(z) to a digital representation Y(z) with respect to a quantization error E(z), which limits the accuracy of the convertor. ...
In this paper, a new sigma delta modulator based on a multiplexed input topology is proposed to decrease power consumption and size in implantable bio-interfacing systems. An opamp sharing technique is employed in order to process several input sequentially. The proposed sigma delta modulator integrates each input separately and stores the integrated value inside a dedicated capacitor. We show that the resulting transfer function of the modulator is equivalent for all channels. The proposed circuit has been implemented in a 180-nm TSMC process. The circuit includes 4 channels and consumes 11.5 μW per channel, provides an ENOB of 7.8 bits, and presents a bandwidth of 10 kHz. The chip area for the proposed design is 150 μm × 135 μm for 4 multiplexed inputs.
... A SDM system can be synthesized, by the proposed methodology, and implemented for GSM/EDGE applications with bandwidth larger the 100kHz and dynamic ranges larger than 60 dB [9], [10]. Table I illustrates the required main OPAMP specifications, which are synthesized by the conventional design methodology. ...
A design methodology of high-order sigma-delta modulators (SDMs) with relaxation of required circuit specifications is proposed to reduce the required power consumption and to be suitable for the nano-scale circuit. According to the proposed design flow, more relaxed circuit specifications can be selected so that designers can maintain system performance. One design example is employed to verify the proposed design flow. Circuit-level simulation reveals that the power consumption is lower under the same system performance compared with a conventional design flow. The circuits are implement with TSMC 90nm 1P9M CMOS process and the measured signal-to-noise distortion ratio (SNDR) is 64.5 dB, with a power consumption of 303μW.
... Multi-rate sampling theory and techniques are presented in various publications and are used for many applications such as sensor measurement systems [1], [2], stiff systems [3], [4] and communication systems [5], [6], [7], [8], and so on. Many solutions have been proposed in the literature, e.g., Han and Ding presented a multi-innovation stochastic gradient parameter identification algorithm for multi-rate multi-input ARX systems [9]; Han et al discussed the auxiliary model based recursive least squares identification for multi-rate multiinput systems [10]. ...
Modeling the receiver end is critical for the overall performance of wireless software defined radio (SDR) systems. This paper investigates the real-time implementation of channel identification for multi-input single-output (MISO) SDR systems. Based on the multi-rate sampling theory, and using the continuous-time system discretization technique with zero-order holds, the channel mapping relationship (a state-space model) between available multi-rate input and output data is set up. The multi-innovation identification theory is applied and a multi-innovation least squares algorithm is presented for the parameter estimation of the receiver end of multi-rate SDR systems based on the multi-rate input-output data.
... A possible solution to palliate this limitation might be using a different sampling frequency for each part (either CT or DT) of the H-ΣΔM, i.e. using a multi-rate system [7]. This approach has been applied to both DT- [8] and CT-ΣΔMs [9]. However, in both cases, the strategy was based on using a lower OverSampling Ratio (OSR) in the front-end parts of the modulator -where most of the power is consumed -and a higher OSR in the subsequent stages or blocks -where the dynamic requirements can be relaxed. ...
... Ideally, the modulator is able to digitize signals with B w from 5MHz to 60MHz and an effective resolution ranging from 9 to 16 bits. According to (8), these specifications can be satisfied for OSR 1 ∈ [8, 128] and p = [2,3,4,5,6]. This is illustrated in Fig. 9 that represents IBN vs. B w (Fig. 9(a)) and IBN vs. OSR 1 (Fig. 9(b)) for different values of p. ...
This chapter discusses the use of hybrid continuous-time /discrete-time fourth-order cascade two-stage 2-2 σΔ modulators for wideband low-power wireless applications. The modulator architecture under study is based on a new concept of multi-rate operation, in which the front-end stage - implemented using continuous-time (Gm-C) integrators - operates at a higher rate than the back-end (switched-capacitor) stage. This strategy benefits from the faster operation of continuous-time circuits while keeping power efficiency and high robustness against circuit element tolerances. A comparison with conventional multi-rate and single-rate (continuous-time) σΔ modulators is carried out based on the impact of main circuit-level error mechanisms, namely: mismatch, finite OTA dc gain and finite gain-bandwidth product. Closed-form analytical expressions are derived for the nonideal in-band noise power of the different architectures under study, demonstrating a good agreement with simulations and showing the benefits of the presented approach. Simulation results show that the proposed modulator is able to operate with a maximum sampling rate of up to 1GHz, digitizing signals with a 44-to-92dB peak signal-to-(noise+distortion) ratio within a programmable 5-to-60MHz bandwidth. © 2012 IFIP International Federation for Information Processing.
In this paper, we study a switch capacitive second-order passive-active sigma-delta modulator with twin benefits of improved speed and lower power dissipation. The comparator block has been on prime focus to improve power and speed. Two design variants of integrators are utilized for improvement. As the filter is simply switch capacitive integrator, there will be high attenuation with lower power dissipation. The second stage integrator is followed by unity gain buffer which does compensation of gain errors and phase errors with respect to ideal integrator transfer function. A 2nd order discrete time sigma-delta modulator will yield exemplary results with using large oversampling ratio. This circuit contains double tail dynamic comparator based on charge sharing scheme to reduce power dissipation and improving speed for the modulator. For circuit level verification, the circuit is simulated using Cadence Virtuoso using GPDK 90 nm CMOS technology. The measurements depicts power dissipation of 1.44 µW, peak Signal to noise ratio & signal to noise and distortion ratio of 84.67 dB and 82.95 Db, respectively, dynamic range is 91.02 dB & ENOB is 13.48 bits using 1 V supply for a 500 Hz sinusoidal signal.
