Figure 5 - uploaded by Dinesh K Bhatia
Content may be subject to copyright.
Illustration of demands for a twoterminal net by (a)Lou and (b)fGREP. Demand assignment for multi-terminal nets by Lou's method is shown in (c)
Source publication
Interconnection planning is becoming an important design issue for
ASICs and large FPGAs. As the technology shrinks and the design density
increases, proper planning of routing resources becomes all the more
important to ensure rapid and feasible design convergence. One of the
most important issues for planning interconnection is the ability to
pre...
Contexts in source publication
Context 1
... placed by Lou's method and fGREP over the rectangular grid has significant differences. Figures 5(a,b) show the distribution of demands made on a grid with two terminals, one in the left bottom and the other in the right top of the grid. Darker regions have higher demands than the lighter ones. ...
Context 2
... method decomposes terminals on a net, and terminal pairs are considered in succession. Figure 5(c) shows how the demands are composed by Lou's method for a MST based decomposition. Regions bound by every pair of two ter- minals are marked in grey and they get some demand val- ues. ...
Context 3
... instance, if the de- tailed router encounters more congestion around the MST, the "escape routes" will be through the other elements in the bounding box. These elements are shown in white in Fig- ure 5(c). These receive zero demand, and thus the estimates will be away from detailed routes whenever escape routes are taken. ...
Similar publications
Low-cost FPGAs have comparable number of Configurable Logic Blocks (CLBs) with respect to resource-rich FPGAs but have much less routing tracks. For CAD tools, this
situation increases the difficulty of successfully mapping a circuit into the low-cost FPGAs. Instead of switching to
resource-rich FPGAs, the designers could employ depopulation-based...
In this paper we present a new clustering technique, based on the multilevel partitioning, for hierarchical FPGAs. The purpose of this technique is to reduce area and power by considering routability in early steps of the CAD flow. We show that this technique can reduce the needed tracks in the routing step by 15% compared with the other packing to...
Citations
... The usage matrices of all these pairs are calculated and summed up to get demand due to the net. The final demand due to all the nets on a region is the sum of the individual demands due to each net similar to Equation 4. In [2], we adapted the Lou's model to FPGA design flows. ...
... The enhancement is based on the observation that the regions in the overlapping segments actually belong to the bounding box of one single net and adding up the demands will just result in overestimation on those regions. This simple enhancement improves the quality of the estimation by as much as 103% compared to the FPGA model proposed in [2]. This is clearly illustrated in the Table 1, where the peak demands estimated by both the methods are compared against the actual peak demands obtained by performing detailed routing using VPR. ...
Interconnect management is a critical design issue for large FPGA based designs. One of the most important issues for planning interconnection is the ability to accurately and efficiently predict the routability of a given design on a given FPGA architecture. The recently proposed routability estimation procedure, fGREP, produced estimates within 3 to 4% of an actual detailed router. Other known routability estimation methods include RISA, Lou's method and Rent's rule based methods. Comparing these methods has been difficult because of the different reporting methods used by the authors. We propose a uniform reporting metric based on comparing the estimates produced with the results of an actual detailed router on both local and global levels. We compare all the above methods using our reporting metric on a large number of benchmark circuits and show that the enhanced fGREP method produces tight estimates that outperform most other techniques.
... * The destination port number d that specifies the port number of the input module. * The bitwidth b that specifies the number of bits of this con- (2,3,1,4,6,8) refers to a connection in Graph G 2 from module 3 (port 1) to module 4 (port 6) that is 8-bits wide. ...
... Each slot will have its own slot interface that remains unchanged for all epochs within a period. 4. Generate module wrappers: Each module is then wrapped with an RDP wrapper (see Section 3.6.2) that maps each bit of data at each port to a slice macro input or output. ...
... + channel2,5 .vcost + channel2,4 .vcost + 1 2 (channel 2,3 .vcost) ...
Modern large scale FPGA designs require interconnect estimation for cutting down the design cycle times. Most of the available
estimation techniques use empirical methods to estimate routability. These methods lack the ability to accurately model back-end
routers and the estimation results produced are not very reliable. We recently proposed a fast and generic routability estimation
method, fGREP [1], that predicts the peak routing demand and the channel occupancies in a given FPGA architecture. The peak demands are within
3 to 4% of actual detailed routing results produced by the well known physical design suite, VPR [2]. In this paper, we observe that, fGREP spends a significant portion of its execution time in estimating the demands for
nets with large number of terminals. We propose a new routability estimation method based on fGREP which offers significant
speedups over fGREP, while maintaining the same high levels of accuracy. The new method is up to 36X faster than fGREP, and on an average is about 102X faster than VPR’s detailed router.
