Fig 2 - uploaded by Chong-Min Kyung
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Illustration of applying CVI to a mask ROM. The candidate strip is assumed to have more unconforming-bit readings.
Source publication
In this paper, we propose a scheme for reducing the power consumption of memory components by conforming memory contents to a precharging value. The scheme is oriented to application to single bitline structure of memory. It selectively stores normal or inverted data to reduce the number of bit accesses that have different values from the prechargi...
Contexts in source publication
Context 1
... are inverted to reduce power consumption. As an exceptional case, FPU con- stant ROM which has more accesses of "1"s than "0"s has 22 noninverted blocks. In conforming vertical-strip inversion (CVI), the block can- didates are columns of basic cells, i.e., vertical strips in a plane block or whole memory. The CVI is applied to ROM as shown in Fig. 2. Each vertical strip consists of basic cells connected with a bitline. All the bit values in a vertical strip are decided to be inverted if and only if the vertical strip has more unconforming bit readings during simulation of the target application. Limit- edly, the strip inversions can be decided by the static analysis of the given ...
Context 2
... overhead of CVI is negligible. What is needed to apply CVI to a mask ROM is just to take inversion for drain contact pattern and polarity of output buffer according to the decision for the strip. Generally, the number of drain contacts and, thus, the total capacitance of a bitline fall off by applying CVI (as noticeable in Fig. 2) as well as the reduction in switching activity of the bitline. Table III shows the simulated power reduction in various mask ROMs, which is caused by CVI assuming CPI has been properly performed, previously. For all the test examples, the amount of power reduction varies from 11.8% to 27.0% without any overhead in area or ...
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Citations
... The bit line and the word line capacitances can be reduced by minimizing the number of 1's in the ROM data since 1's are implemented as transistors of which the junction capacitance and the gate capacitance are the sources of bit line and word line capacitances [2]. In [3] and [4], data encoding methods that invert column or row data to reduce the number of 1's in ROM data are proposed, respectively. In those methods, if the data contains more 1's than 0's, row or column data is inverted to reduce the number of 1's and hence, the load capacitance. ...
... In those methods, if the data contains more 1's than 0's, row or column data is inverted to reduce the number of 1's and hence, the load capacitance. In column inversion [3], a bit line is implemented with the inverted column data when the bit line has more 1's than 0's. An inverter is added to each inverted bit line. ...
... To compare the power consumption reductions achieved by the column inversion [3], the row inversion [4], the word line collapsing [5] and the proposed encoding, we model ROMs on a schematic level using 0.18 μm CMOS process with the data obtained by applying the encodings and the transformation to the coefficients of FIR filters. We simulate the ROM models and estimate power consumptions by using Cadence Spectre that is a transistor-level circuit simulator. ...
This paper propose a new ROM data encoding method that takes into account of a sequential access pattern to reduce the power consumption in ROMs used in applications such as FIR filters that access the ROM sequentially. In the proposed encoding method, the number of 1's, of which the increment leads to the increase of the power consumption, is reduced by applying an exclusive-or (XOR) operation to a bit pair composed of two consecutive bits in a bit line. The encoded data can be decoded by using XOR gates and D flip-flops, which are usually used in digital systems for synchronization and glitch suppression. By applying the proposed encoding method to coefficient ROMs of FIR filters designed by using various design methods, we can achieve average reduction of 43.7% over the unencoded original data in the power consumption, which is larger reduction than those achieved by previous methods.
Various input addresses and accessed code-patterns of a via-programming read only memory (ROM) cause substantial fluctuations in peak current and supply noise across cycles. This work analyzes the fluctuations in the supply noise that are associated with the pattern-dependent current profile of embedded via-programming ROM on a QFN package with various decoupling capacitances. A pattern-insensitive (PI) technique is developed for via-programming ROM to reduce both fluctuations of peak current and cycle current across various input addresses and accessed code-patterns. The PI technique involves the arranging of the data patterns of a ROM-code and the adjustment of the structures of row decoders and peripheral circuits. Experiments based on the designed test-setup on fabricated 0.25 mum 256 kb ROM macros demonstrate the fluctuation in peak current of conventional ROM and its reduction by the PI technique. The fluctuations of measured peak and cycle currents of PI-ROM are only 0.7% and 13.1% of those of conventional ROM. The PI-ROM also has a 94.5% lower standby current than conventional ROM.
A novel micro-power current sense amplifier employing a cross-coupled current-mirror configuration is presented. The circuit is designed for low-voltage low-power SRAM applications. Its sensing speed is independent of the bit-line capacitances and is almost insensitive to the data-line capacitances. Extensive post-layout simulation results based on a 1.8 V/0.18 μm CMOS technology from Chartered Semiconductor Manufacturing Ltd. (CHRT) have verified that the new sense amplifier promises a much sought-after power-efficient advantage and a note-worthy power-delay product superiority over the conventional and recently reported sense amplifier circuits. These attributes of the proposed sense amplifier make it judiciously appropriate for use in the contemporary high-complexity regime, which incessantly craves for low-power characteristics.
