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INL(k) estimation error with P=32 and 5-bit dithering DAC, 14 bits DAC under test
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On-chip testing of high-resolution high-speed DACs is extremely challenging because of the stringent requirements on the accuracy, speed and cost of the measurement circuits. This work proposed a new on-chip strategy for DAC linearity testing applying the proposed deterministic dynamic element matching (DDEM) technique. Low-accuracy two-step flash...
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Context 1
... SIMULATION RESULTS The proposed DDEM algorithm and test scheme are verified by numerical simulation. In simulation, a 14-bit DAC is modeled as the device under test. Its INL(k)s are shown in the top plot of Fig. 4. The test system has a 6-bit DDEM first stage, a 6-bit second stage and a 5-bit dithering DAC. The linearity of the coarse stage is less than 7 bits with the INL of 0.38LSB. The fine stage and the dithering DAC are nearly 6-bit linear. The standard deviations of comparator offsets in two stages are 0.3LSB of the first and second stages ...
Context 2
... is 32. A noise is added to the input of the DDEM ADC with a standard deviation equal to 1 LSB at the 14-bit level. With P=32, the quantization error is calculated to be less than 16-bit level. The test performance of the specified system is roughly equivalent to n test =6+5+5=16 bits. Therefore, it should be capable of testing a 14-bit DAC. Fig. 4 shows that with the above configuration the maximum INL(k) estimation error is about 0.5LSB at 14-bit level and the INL estimation error is ...
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Citations
... There are four main parameters in DAC static test: offset error, gain error, integral nonlinearity (INL) error and differential nonlinearity (DNL) error. There are several BIST methods to test static parameters of a DAC [1][2][3][4][5]: Reference [1] uses the method of device dynamic matching to complete the static error test of DAC. This method can test the DAC with high resolution and high speed. ...
... This method can make the accuracy of BIST test very high but it requires some complex modules and makes the cost too high [2] . Reference [3] uses a large number of reference voltages to realize static test, and BIST compares the output voltage of DAC to be tested with the reference voltage. This method is easy to be implemented, but it requires a large number of reference voltages [3] . ...
... Reference [3] uses a large number of reference voltages to realize static test, and BIST compares the output voltage of DAC to be tested with the reference voltage. This method is easy to be implemented, but it requires a large number of reference voltages [3] . Reference [4] reduces the number of reference voltage when testing static parameters, but this method requires a lot of control signals and a lot of hardware support [4] . ...
A new BIST (Built-In Self-Test) method to test static parameters of a DAC (Digital to Analog Converter) is proposed in this paper. The BIST method employs a ramp generator and two voltage references to test static parameters of a DAC: offset error, gain error, INL (Integral Non-Linearity) and DNL (Differential Non-Linearity). The optimization of calculating static parameters and the components sharing can reduce the BIST circuitry. The simulation result shows that the method is able to detect the static errors with the simple BIST structure..
... In these cases, the voltage values must be necessarily characterized in correspondence to any of the codes. A possible solution to reduce static testing duration in such DAC architectures consists in saving time for the single measurement by means of built-in self-test schemes [4][5][6]. In particular, a built-in self-test scheme for DAC static testing is suggested in [7] with a low resolution onboard digitizer, in place of a highly accurate voltmeter. ...
... The INL value, corresponding to the input code ∈ , is evaluated by following the (4). The relation between the whole INL curve and the INL evaluated only on the selected codes can be modeled by a linear transformation taking into account the selection process. ...
This paper proposes an innovative method for Integral Nonlinearity (INL) testing, that allows to measure the voltage corresponding only to a subset of all the codes of Digital-to-Analog Converters (DAC), shortening the duration of static characterization. The method operates, in fact, a pseudo-random selection of DAC codes to be tested but, through Compressed Sensing, it is able to recover the INL value for all the codes. The proposed method is experimentally evaluated on two DACs with different architectures and thus with different trends of the INL curve. In the performed tests, the recovered curve results very close to the INL curve obtained by the standard approach, while allowing a considerable time saving.
... However, the accuracy of the DAC INL/DNL estimation is limited and the test time is long. In [5], the authors developed a circuit with deterministic dynamic element matching (DDEM) ADC and a dithering DAC to test the DAC. It is capable of testing a 14-bit DAC with ADC at 6-bit linearity. ...
... However, the DDEM (deterministic dynamic element matching) technique arranges matching-sensitive elements to generate appropriate outputs. In [7], a DDEM method with dithering was investigated for high-performance DAC testing with low-resolution flash ADCs. The method uses resistor string that 2 n resistors and 2 n + 1 switches in series. ...
... However, the method still produces mismatch errors because switches between voltage source and resistors still produce the errors. [7,8] used low-cost DDEM structures to test ADCs or DACs. While the DDEM ADC structure has been improved over many years, it still has hardware overhead problems and mismatch errors due to switch effects. ...
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... In [3], a DDEM method was applied to current steering DACs for high-resolution ADC testing. In [4], the DDEM method with dithering technique was investigated for high-performance DAC testing with low-resolution flash ADCs. [3] and [4] use low-cost DDEM structures for the testing of DACs but they need many resistors and switches. ...
... In [4], the DDEM method with dithering technique was investigated for high-performance DAC testing with low-resolution flash ADCs. [3] and [4] use low-cost DDEM structures for the testing of DACs but they need many resistors and switches. This brings high hardware overhead and voltage drop problems by switch effects. ...
... It can be imagined that the resistor strings have poor linearity. Table 1 shows the resource usage comparison with previous work [4] which is proposed recently. The previous work presents the conventional flash DDEM ADCs with a resistor loop while the resistances of resistors are all 1. ...
.kr for the testing of DACs. In this work, the proposed method make that resistors in a resistor string have different lengths by a merging operation. Accuracy of the proposed method is proven by theoretical analysis. The experimental results show that the proposed method reduces the usage of resources over 17%. resolution flash ADCs. (3) and (4) use low-cost DDEM structures for the testing of DACs but they need many resistors and switches. This brings high hardware overhead and voltage drop problems by switch effects. In this paper, we propose a new algorithm which reduces the number of resistors and switches. It makes DDEM ADCs more effective and practical. The rest of this paper is organized as follows : In Section II, the conventional DDEM ADC structure is shown. The proposed BIST method is explained in Section III and the experimental results are discussed in Section IV. Finally, the concluding remarks are in Section V.
... In a static test, static parameters such as offset, gain, INL and DNL errors are calculated. Several BIST methods have been proposed to test static parameters of a DAC [3][4][5][6][7]. In [3], a linearity test method is proposed using DD EM(Deterministic Dynamic Element Matching) ADC with dithering. ...
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kr Abstract- A new BIST(Built-In Self-Test) scheme to test static parameters of a DAC(Digital-to-A nalog Converter) is proposed in this paper. The proposed BIST employs a ramp generator and two voltage references to calculate static parameters of a DAC such as offset, gain, INL(Integral Non-Linearity) and DNL(Differential Non-Linearity). The optimization of calculating static parameters and the element sharing can reduce the BIST circuitry. The simulation results which validate our method are able to detect the linearity errors with the simple hardware architecture.
... However, [4] and [5] require high area overhead and complex modules for implementation. In [6] and [7], the linearity of DAC is calculated using one or more analog-to-digital converters (ADCs) with the same resolution to the DAC under test. In a TFT-LCD source driver IC, there are hundreds or thousands of DACs in parallel. ...
... The methods of [4] and [5] which cause excessive hardware overhead also would have a problem if they were applied into multiple DACs. In addition, schemes in [6] and [7] cause the serious area overhead problem. As a result, it is difficult to apply conventional DAC testing methods into a source driver IC, because the application requires hundreds or thousands of DAC BISTs while the conventional methods aim at a single DAC. ...
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