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HV solutions in standard CMOS: (a) LDSD or symmetric LDD; (b) asymmetric LDD source structure; (c) Field-ring technique; (d) gate-shift technique; (e) inclusion of a metal field-plate.
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This paper presents trends on CMOS high-voltage techniques for power integrated circuits (PICs). Several fully CMOS compatible drain engineering techniques will be presented. Experimental devices were fabricated in standard CMOS processes from three different lithography generations (2, 0.7 and 0.5 μm) without resorting to any extra processing step...
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... CMOS compatible extended drain devices can be derived from most CMOS processes, taking advantage of the presence of the lightly doped n-well (p-well in an n-substrate technology). The first lightly doped drain (LDD) type MOS structures were proposed in 1987 [15]. As can be seen in Fig. 2a, in the symmetric LDD NMOS, both drain and source are composed by a contact/n þ /n-well sequence. Gate electrode (polysilicon/active area masks intersection) overlaps both n-well lateral diffusion and a fraction of polysilicon superposes the thick oxide (where polysilicon and active area masks intersection is void). Transistor channel ...
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... order to reduce ON-resistance, a low-side device or asymmetric LDD can be designed, with a source structure as shown in Fig. 2b. This typology is dependent on the application in view. Asymmetric LDD is less prone to punch through, due to its much shorter n þ implant lateral profile, when compared to the ...
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... optimisation of ON-resistance can also be accom- plished through L GD reduction (Fig. 2a), if possible without BV degradation. Reduction of L GD shortens drift path and increases the accumulation path, thus affecting device parasitics: ON-resistance is reduced but at the expense of an increase in gate -drain overlap capacitance [17]. For a specific technology, tradeoffs and optimisation of L GD and L drawn lengths should be ...
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... -drain overlap capacitance [17]. For a specific technology, tradeoffs and optimisation of L GD and L drawn lengths should be evaluated with the help of 2D simulation, finding out the shortest cell pitch for the basic cell. Additional ON-resistance reduction can be obtained by adjustment of the polysilicon fraction overlapping field oxide (FOX) (Fig. 2a). Geometric design rules compel this overlap to a limit. Therefore, designers should choose it as the longest as possible to further reduce drift path, although at the cost of a slight increase in gate -drain overlap capacitance (actually, very small since FOX thickness is much greater than gate ...
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... surface, aligned with the gate edge. Therefore, it is expected that the inclusion of a p þ field ring [18] at this critical spot (Fig. 2c) will promote a field-free region, due to the depletion of the n-well/p þ junction, with the corresponding increase in drain voltage breakdown. In fact, since p þ implant mask is the gate mask itself, gate edge is positioned over p þ field implant lateral scattering (Fig. ...
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... that the inclusion of a p þ field ring [18] at this critical spot (Fig. 2c) will promote a field-free region, due to the depletion of the n-well/p þ junction, with the corresponding increase in drain voltage breakdown. In fact, since p þ implant mask is the gate mask itself, gate edge is positioned over p þ field implant lateral scattering (Fig. ...
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... gate-shift HV technique is also fully CMOS compatible [17]. In the gate-shifted LDD (GS-LDD) device [11,19], the borders of n-well and gate masks are kept apart by the length L GS , the continuity of the current path being ensured by the N-well lateral diffusion (Fig. 2d). As the concentration of the lateral diffusion decreases from a maximum at n-well surface towards the channel concen- tration, a BV improvement is attained when L GS is ...
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... insertion of a metal field plate connected to source and overlapping the device drain drift region (Fig. 2e) was found to be not significant to improve ON-resistance and BV, especially for the classical LDD cases. Reported results for a GS-LDD with L GS ¼ 1:2 mm showed a BV improve- ment of only 3 V and an ON-resistance reduction less than 3% [19]. Besides, this technique reduces versatility in layout interconnection strategy, which is a ...
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Citations
... However, emerging MEMS technologies such as electrostatic 2 and field-effect actuators 3-5 rely on high voltages, typically between hundreds and thousands of volts. Although high-voltage CMOS processes do exist, their cost remains prohibitive 6 , forming a bottleneck in the development of prototyping high-voltage actuator arrays. Current solutions for high-voltage control for such arrays rely on individual wiring of each actuator to a single off-chip high-voltage switch, such as a mechanical relay 7 , a high-voltage MOSFET 8 , or a photoconductive semiconductor switch 9 . ...
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... However, emerging MEMS technologies such as electrostatic 2 and field-effect actuators 3-5 rely on high-voltages, typically between hundreds and thousands of volts. Although high-voltage CMOS processes do exist, their cost remains prohibitive 6 , forming a bottleneck in the development of prototyping of high-voltage actuator arrays. Current solutions for high-voltage control for such arrays rely on individual wiring of each actuator to a single off-chip high-voltage switch, such as a mechanical relay 7 , a high-voltage MOSFET 8 , or a photoconductive semiconductor switch 9 . ...
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... ASICs developed in such processes cannot handle negative voltages (lower than the substrate potential) and cannot integrate floating diodes [19]. The maximum current that these HV devices can handle is limited to a few hundred mA, and the maximum operating voltages are typically no larger than 50 V, with rare exceptions going up to 100 V-see [20][21][22]. ...
This paper presents a novel topology for multipurpose drivers for MEMS sensors and actuators, suitable for integration in low-cost high-voltage (HV) CMOS processes, without a triple well. The driver output voltage, VMEMS, can be programmed over a wide, symmetrical range of positive and negative values, with the maximum output voltage being limited only by the maximum drain-source voltage that the HV transistors can handle. The driver is also able to short its output to the ground line and to leave it floating. It comprises generators for large positive and negative voltages followed by an LDO for each polarity that ensures that VMEMS has a well-controlled level and a very low ripple. The LDOs also help implement the grounded- and floating-output operating modes. Most of the required circuitry is integrated within a HV CMOS ASIC: the drivers for the large voltage generators, the error amplifiers of the LDOs, the DAC used to program the VMEMS level, and their support circuits. Thus, only the power stages of the large voltage generators, the pass transistors of the LDOs and two resistors for the LDO feedback network are discrete. A suitable configuration was devised for the latter that allows for the external resistor network to be shared by the two LDOs and prevents negative voltages from developing at the ASIC pins. Two circuit implementations of the proposed topology, designed in a low-cost 0.18 μm HV CMOS process, are presented in some detail. Simulation results demonstrate that they realize the required operating modes and provide VMEMS voltages programmable with steps of 100 mV or 200 mV, between -20 V and +20 V or between −45 V and +45 V, respectively. The output voltage ripple is relatively small, just 3.4 mVpkpk for the first implementation and 17 mVpkpk for the second. Therefore, both circuits are suitable for biasing and controlling a wide range of MEMS devices, including MEMS mirrors used in applications such as endoscopic optical coherence tomography.
... The extended drain is usually the suitable technique to attain HV ( 5 V) devices in CMOS, since its implementation is fully compatible with the foundry design rules and fabrication process. Other CMOS compatible techniques are also available in the literature and could be used to compose the power part of the educational tool [10], [12]. ...
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... Another approach for smart power integration for low power applications involves the extended drain technique [3] to perform High-Voltage (HV) NMOS in a digital or mixed-mode core CMOS process with no extra processing. Previous works [4,5] indicated another fully CMOS compatible drain engineering technique-the gate-shifting-useful to increase extended drain transistors breakdown voltages fabricated in CMOS processes with long term diffused wells. ...
... In fact, when compared with BCD, BiCMOS or dedicated smart power technologies, CMOS is the less complex of all, due to the reduced number of masks and specific implant regions. On the other hand, the fully CMOS compatible gate-shifting technique was found efficient to perform breakdown voltage increase in GS-LDD devices fabricated in diffused wells CMOS processes [4,5]. However, the implementation of GS-LDD devices in a twin and fully implanted wells CMOS process is not so obvious. ...
This paper discusses the viability of using last generation CMOS technology to develop a High-Voltage NMOS library for smart power integration.Breakdown voltages of the order of 30 V can be achieved for Gate-Shifted extended drain NMOS devices fabricated in a fully implanted, twin-well, 0.5 μm CMOS core process, aimed for mixed-mode applications, without process modification or any additional mask.The trade-offs of using high overdrive voltages, above nominal supply, to reduce On-resistance is also discussed. According to experiments on prototypes, devices under excessive overdrive voltages over long periods revealed threshold voltage and transconductance variations, due to gate oxide degradation.
... Nevertheless, an existing low-voltage technology should desirably be used for the fabrication of Power Integrated Circuits (PICs) in order to reduce development efforts and time. One of the main advantages of this approach is that all the existing standard cells and libraries can be used in designing the low voltage parts of the circuit [5]. Significant efforts have been carried out in the past years to develop CMOS compatible high-voltage devices and integrate them into existing low-voltage VLSI processes [6 -9]. ...
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... It was proven elsewhere [5] and [6] that it is possible to reach the same objective using low cost standard digital CMOS technologies, although in same cases minor modifications were introduced in the process technology such as, dual thin oxides or deep nwell to accommodate p+ diffusion allowing the creation of LDMOS isolated transistors. Other techniques also use the manipulation of process masks in order to reach the same objective [7]. The transistor topology now presented for high power output transistors was first considered for IO pad cells due for its compact, comparable ESD robustness, and lower drain parasitic capacitance [8]. ...
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... These basic switching cells are normally inspired on the classical extended drain engineering technique suggested by Dolny et al. [1] and adapted by Parpia et al. [2] for a CMOS compatible solution with no modification on process steps. Recent works on a 2 µm and a 0,7 µm CMOS digital processes indicate the gate-shifting drain engineering technique as an effective approach to further increase the breakdown voltage of these extended drain or lightly-doped drain (LDD) devices [3], [4]. ...
... In fact, when compared with BCD, BiCMOS or dedicated smart power technologies, CMOS is the less complex of all, due to the reduced number of masks and specific implant regions. On the other hand, the fully CMOS compatible gate-shifting technique was found efficient to perform breakdown voltage increase in GS-LDD devices fabricated in diffused wells CMOS processes [3], [4]. However, the implementation of GS-LDD devices in a twin and fully implanted wells CMOS process to improve breakdown is not so obvious. ...
Experimental results presented in this paper confirm gate-shifting as an efficient drain engineering technique to increase the breakdown voltage of extended drain high-voltage NMOS transistors to be fabricated in last generation CMOS processes. Breakdown voltages of the order of 30 V can be achieved for gate-shifted LDD NMOS devices fabricated in a fully implanted twin-well 0.5 μm CMOS process, aimed for digital applications, without process modification or any additional mask.
