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HMC block diagram formed by 32 vaults with 8 banks each. Adapted from [5]. 

HMC block diagram formed by 32 vaults with 8 banks each. Adapted from [5]. 

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Fig. 1. DDR 3 x8 functional block diagram of a single device. Adapted...
Fig. 2. HMC block diagram formed by 32 vaults with 8 banks each....
Fig. 3. Performance results for SPEC-CPU2006. 
Fig. 5. HMC speedup and contiguity results for SPEC-CPU2006. 
+1 Fig. 6. Performance results for SPEC-OMP2001. 
HMC and DDR performance trade-offs
Conference Paper
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  • Apr 2015
The evolution of main memories, from SDR to the current DDR, presents multiple technological breakthroughs, but still far from the requirements of the processors. With the advent of Hybrid Memory Cube (HMC), a promise of high bandwidth with low energy consumption and less area may provide better efficiency than the traditional DDR modules. This is...
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... HMC memories are composed of up to 8 layers of DRAM memory and one logical layer per vault, all integrated in the same device. Figure 2 illus- trates the main HMC architectural details. The three main components inside the HMC are the following: Memory vaults: HMC memories store data on contiguous row buffers, inter- leaving throw the memory vaults and then to memory banks inside the vaults. ...