Fig 2
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Additional check bits, which are commonly attached to the message’s input data, are normally used to minimize the error
during data transmission. The receiver system implements a checking algorithm to determine if an error was occurred in
the received data. This algorithm will correct a corrupted bit and recover the original message. An enhanced er...
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Cyclic redundancy check (CRC) is a well-known error detection code that is widely used in Ethernet, PCIe, and other transmission protocols. The existing FPGA-based implementation solutions are faced with the problem of excessive resource utilization in high-performance scenarios. The padding zeros problem and the introduction of programmability fur...
Cyclic redundancy check (CRC) is a well-known error detection code that is widely used in Ethernet, PCIe, and other transmission protocols. The existing FPGA-based implementation solutions are faced with the problem of excessive resource utilization in high-performance scenarios. The padding zeros problem and the introduction of programmability fur...
Cyclic redundancy check (CRC) is a well-known error detection code that is widely used in Ethernet, PCIe, and other transmission protocols. The existing FPGA-based implementation solutions are faced with the problem of excessive resource utilization in high-performance scenarios. The padding zeros problem and the introduction of programmability fur...
Citations
... Work [6] continued the study of codes that have the properties of detecting and correcting errors. An algorithm for reducing the number of redundant bits when constructing an extended error detection and correction code is proposed. ...
The object of the study is the IOT system for monitoring the state of objects. The problem being solved is the development of an innovative method of detecting and correcting data transmission errors in the networks of Internet of Things systems. The essence of the results is that a method of detecting and correcting multiple transmission errors during byte-by-byte transmission of a block of information has been developed. The method is distinguished by an original coding scheme, which involves the calculation of control bits, as well as the shuffling of block bits by performing bit shift operations. The peculiarity of the method is that any bit can be distorted when transmitting a code word, but it belongs to different code combinations of the Hamming code. This allows multiple data transmission errors to be detected and corrected during decoding, and multiple errors of different bytes belonging to the same block can be corrected. Simple algorithms for encoding and decoding procedures have been developed, and programs for information block encoding procedures and decoding procedures with error detection and correction have been developed. A software model of the data transmission channel was also developed with the possibility of introducing multiple errors when simulating the data transmission process. All programs are developed in Python, although other languages are possible. An experiment was conducted using the developed software model of the data transmission channel. The efficiency of the developed method has been experimentally confirmed and it has been proven that its use increases the immunity of the data transmission channel. This is due to the fact that the developed method allows detecting and correcting all code word transmission errors with a multiplicity from 1 to 8, which was confirmed experimentally. The main field of use of the developed method is considered to be IoT system networks. First of all, systems for monitoring the state of objects
... Additionally, a shift register can perform mathematical operations such as addition, data shifting, and multiplication. As a result, they are mainly employed to store and transfer digital data (Baskoro et al., 2018;Tolentino et al., 2018Tolentino et al., , 2019. The most challenging aspect of an IC designer's job is designing a digital chip that can perform at the highest throughput while still using little power, resulting in more conserved energy. ...
By keeping the very same transmission rate, a scheme is provided by DETFF (double-edge triggered flip-flops) for power dissipation reduction. As a result, they are suitable for use as shift registers. This investigation discussed various previous DETFF designs and demonstrated a new DETFF circuit applied to construct an 8-bit low-power shift register. This study makes a significant contribution by using two parallel data paths that operate in a single clock's opposing phases where an inverted input trigger is unnecessary. TSMC 90-nm complementary metal-oxide semiconductor (CMOS) technology was used to implement the proposed shift register. Comparing the proposed DETFF with prior works, it has fewer transistor counts since the negated input trigger and auxiliary devices were removed, resulting in lower area cost and lower power dissipation. At 100 MHz clock frequency and lower supply voltage of 1.0 V, it demonstrates a power consumption of 3.352 mW on silicon, making it suitable for low-power applications. Lastly, it has the best performance compared with prior works speaking of larger scale, as demonstrated by the chip's functionality and jitter measurement at the maximum frequency of 200 MHz.
... Renewable energy aims to be a reliable power supply, offering fuel diversification, maintaining energy security, minimizing the risk of fuel spills, and lowering the demand for imported fuels. Nowadays, there are numerous domains of application that utilize renewable energy sources, such as medical [1], driverless cars [2], and wireless wearables [3]. As a renewable energy source, solar energy produces solar power, converted into electricity-i.e., solar cells, also called photovoltaic cells that convert sunlight into electricity [4][5][6]. ...
Infrared thermography is the science of measuring the infrared energy emitted by an object, translating it to apparent temperature variance, and displaying the result as an infrared image. Significantly, acquiring thermal images delivers distinctive levels of temperature differences in solar panels that correspond to their health status, which is beneficial for the early detection of defects. The proposed algorithm aims to analyze the thermal solar panel images. The acquired thermal solar panel images were segmented into solar cell sizes to provide more detailed information by region or cell area instead of the entire solar panel. This paper uses both the image histogram information and its corresponding cumulative distribution function (CDF), useful for image analysis. The acquired thermal solar panel images are enhanced using grayscale, histogram equalization, and adaptive histogram equalization to represent a domain that is easier to analyze. The experimental results reveal that the extraction results of thermal images provide better histogram and CDF features. Furthermore, the proposed scheme includes the convolutional neural network (CNN) for classifying the enhanced images, which shows that a 97% accuracy of classification was achieved. The proposed scheme could promote different thermal image applications—for example, non-physical visual recognition and fault detection analysis.
This study introduces a novel approach to address the limitations observed in existing random number generator (RNG) designs, focusing on the resolution for insufficiently covered problem statements and study purposes. In response to these challenges, we propose a high-throughput metastable-based RNG tailored for cryptography applications. Our design is featured with a two-layer transient effect ring oscillator (TERO) architecture, meticulously crafted to mitigate the locking phenomenon and enhance RNG randomness. Leveraging interleaved two-layer TEROs, realised through NAND and NOR SR latches, our RNG achieves unpredictable irregular sampling, crucial for cryptographic applications. To further enhance irregular sampling, the first layer of the RNG employs a multiplexer that selects inputs randomly. This multiplexer is governed by selection signals generated by the second layer of the RNG, ensuring superior randomness. Implemented using TSMC 40-nm CMOS process, our RNG passed the FIPS 140–1 randomness test at a clock frequency of 100 MHz, boasting a remarkable throughput of 50 Mbps. This study represents a significant advancement in RNG technology, addressing previous shortcomings and paving the way for high-speed communication systems’ secure cryptographic applications.
A double-edge triggered flip-flop (DETFF) has the distinct ability to latch data at either the rising or the falling edge of the edge unlike the single-edge triggered flip-flop (SETFF). The proposed DETFF uses parallel dual paths that work without the need of keepers for input signal boost and an inverting clock for the opposite phase operation. A Schmitt trigger replaced the conventional feedback inverter with keeper in the DETFF, since the feedback inverter may lead to metastability which can affect the output at unexpected timing. The said DETFF was implemented in a 32-bit shift register using TSMC 40-nm CMOS for functionality testing. At a load capacitance of 60 pF, 31.71% power consumption decrease and 43.57% T c-q delay reduction were exhibited by the proposed shift register as shown by the post-layout simulation results. It has the best normalized energy per bit normalized power, and normalized delay per bit among prior works.
