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Embedded processors with fixed architecture have disadvantages: they are neither reusable nor are they flexible enough to match the specific needs of different application domains. The main technique employed to accelerate instruction execution in such processors is to add fixed hardware units, which may be useless for some applications yet insuffi...
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Register file is one of the vital and energy consuming parts inside microprocessor. Many studies show that it is one of the hot spots on the chip. It is also observed by many researchers that many of the produced values in a processor are narrow. By using the narrow values, register files can store fewer bits and may be designed to need less static...
Citations
... An optimized run-time profiling algorithm is a major step towards a self-reconfigurable embedded processor architecture [1]. Run-time profiling answers many critical questions like: Does the running algorithm need hardware acceleration? ...
... In a previous paper [1] we used the terms "Pessimistic" and "Preparation Mode" profiling to denote two distinguished approaches to run-time profiling in the context of run-time reconfigurable processors. For the sake of completeness, another approach, called "optimistic" will be investigated in addition to our "pessimistic" approach. ...
Embedded processors are expected to immigrate towards self-reconfigurable architectures, and in the near future, the self-reconfiguration concept will be able to support revolutionary architectural innovations. The research described in this paper is a continuation of our previous work [1]. In [1], the advantage of the - so called - pessimistic run-time profiling approach was demonstrated and compared to preparation mode profiling and optimistic run-time profiling. Using pessimistic run-time profiling, a 36.09 % reduction in execution time was achieved compared to 23.02% in the optimistic run-time profiling case. These results were obtained using the “High Pass Grey-Scale Filter” benchmark as our case study [2]. Here, we extend the previous results to include a hardware implementation of pessimistic run-time profiling. Due to the parallel execution of run-time profiling and the running algorithm, execution time reduction was increased to 57.73% on the same benchmark. Total energy consumed by our hardware implementation was only 54 Pj, and some 1,371 gates were added to the design. These two figures represent approximately 1.4×10-5 % and 1.828 % increase in energy consumption and gate count, respectively, as compared to the pessimistic-accelerated case and main core gate count. The hardware run-time profiling unit introduced here is based on the "predetermined basic regions detection" philosophy, and can operate at a maximum frequency of approximately 278 MHz for this particular case study. Profiling each critical region consumes less than 3.6 ns and executes in parallel with the decode stage of the main processor instruction pipeline. Hardware pessimistic run-time profiling is, thus, able to achieve the same speedup of the full acceleration case - in which no profiling is used - with only a marginal increase in area and energy consumption as compared to the non-accelerated case. All results were obtained using Ten silica [3] and Xi- - linx [4] Tools.
