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![Fig. 2. A Conventional Transistor Level Realization of a Full Adder [14].](profile/Adib-Abrishamifar/publication/224598025/figure/fig2/AS:340499945803777@1458192921256/A-Conventional-Transistor-Level-Realization-of-a-Full-Adder-14_Q320.jpg)
In this paper a new high speed and low power adder is presented. The circuit uses a hybrid concept of analog and digital circuit design to propagate the carry and so achieve a Full Adder with 78 ps delay and 7.26 muW of power consumption. SPICE Simulations performed on the 0.18 mum TSMC Technology demonstrates the average improvement of 159%, 184%...
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... However, recently, designers used both concepts of analog and digital circuit design to achieve hybrid processors with positive properties of both analog and digital circuits [9][10][11][12][13]. In this paper also we've used hybrid analog-digital circuits to make and adder with better properties (i.e. with reduced delay and power consumption). Fig. 1. demonstrates general structure of a full adder; consisting of two half adders and an OR gate. Regardless of implementation details of half adders, they've to include at least one gate. With a supposed minimum delay time of t for the gates, simply critical path (the path with maximum delay which determines the overall delay of full ...
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... of implementation details of half adders, they've to include at least one gate. With a supposed minimum delay time of t for the gates, simply critical path (the path with maximum delay which determines the overall delay of full adder) can be recognized; it's "carry out" path with 3t delay (shown in Fig.1). ...
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... have a better comprehension about the achieved results, they were compared with four recent papers. Graphic comparisons of Delay and Power Consumption are illustrated in Fig. 9 and Fig. 10, respectively. It should be mentioned again that as discussed before, the carry propagation delay is determinant in overall delay and so delay comparisons have been made among carry propagation delays. It's conspicuous that except the proposed circuit, there is only one work with less than 100 ps delay and in comparison to that work we ...
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Citations
... On similar lines analysis high speed radix 4 multiplier using Shannon adder that is suitable of digital signal processor (DSP) applications is presented in [2]. A similar sort of hybrid adder using analog and digital circuits is presented in [3]. The design of adders that are aimed to achieve power savings is given in [4], [5]. ...
span>High speed and competent addition of various operands is an essential operation in the design any computational unit. The swiftness and power competence of multiplier circuits plays vital role in enlightening the overall performance of microprocessors. Multipliers play crucial role in the design of arithmetic logic unit (ALU) or any digital signal processor (DSP) that are effectively employed for filtering and convolution operations. The process of multiplication either binary numbers or fixed-point numbers yields in enormous partial products that are to be added to get final product. These partial products in number and the process of summing up partial products dictate the latency and power consumption of the multiplier design. Here, we present a novel binary counter design that hires stacking circuits, that groups all logic “1” bits as one, followed by a novel symmetric method to merge pairs of 3-bit stacks into 6-bit stacks and then changes them to binary counts. This results in drastic improvements in power and area utilization of the multiplier. Additionally, this paper also focuses on implementation of novel approximate compressor and exploits the same for the design of approximate multipliers that can be effectively employed in any electronic systems that are characterized by power and speed constraints.</span
Low-power and high-speed calculation is very important nowadays for energy-efficient demand of electronic devices. With the usage of ANT (All-N-transistor) logic, the speed constraint caused by PMOS transistors can be overcome through an auxiliary current path across NMOS transistors. This study presents a 800-MHz 28.8-mW 8-bit carry look-ahead adder (CLA) using ANT logic implemented on chip. FinFET technology is utilized to improve carrier mobility and increase device speed. R-C parasitic capacitance in FinFET devices is considered in the analysis of the delay time for the 8-bit CLA to improve PDP (power-delay product). The proposed design is implemented in 16-nm FinFET process with core area of 206.403 ×\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\times $$\end{document} 152.506 μ\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$\upmu $$\end{document}m2\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$^2$$\end{document}. It has the lowest normalized PDP at 60 pF load by far.
