Functional Block Diagram for the True Time Delay Beamformer Firmware Design

Functional Block Diagram for the True Time Delay Beamformer Firmware Design

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This paper presents how to simultaneously achieve elemental sub-Nyquist sampling and true-time-delay (TTD) beamforming using a contemporary RF system-on-a-chip (RFSoC) by outlining the development of a 1.6 GHz S-band phased array system implemented using a Xilinx 8-channel 4 GSPS RFSoC. RFSoCs integrate a high speed analog-to-digital converters (AD...

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... functional block diagram for the custom FPGA image is provided in Figure 8. As discussed in Sections II-B and II-C, sub-Nyquist-sampled TTD beamforming requires Fig. 9. Interleaved FIR Filter Diagram: parallel processing required to support full digital bandwidth an integer-sample delay, fractional-sample delay, and phase shifter for channel compensation. ...

Citations

... In this section, we will utilize SFGs to elaborate on Thiran fractional delays for twiddle filter realization. Although a direct-form realization of the digital DVM beamformer [50] can be realized using Thiran filters for realizing each fractional sample delay, we proposed to reduce the computational complexity of the multi-beam beamformer by exploiting sparse factorization of the DVM in [7] followed by the fast DVM algorithm, i.e., ddvm. However, the SFGs in [7] are continuous-time and realized as analog microwave circuits. ...
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The ability to sense propagating electromagnetic plane waves based on their directions of arrival (DOAs) is fundamental to a range of radio frequency (RF) sensing, communications, and imaging applications. This paper introduces an algorithm for the wideband true time delay digital delay Vandermonde matrix (DVM), utilizing Thiran fractional delays that are useful for realizing RF sensors having multiple look DOA support. The digital DVM algorithm leverages sparse matrix factorization to yield multiple simultaneous RF beams for low-complexity sensing applications. Consequently, the proposed algorithm offers a reduction in circuit complexity for multi-beam digital wideband beamforming systems employing Thiran fractional delays. Unlike finite impulse response filter-based approaches which are wideband but of a high filter order, the Thiran filters trade usable bandwidth in favor of low-complexity circuits. The phase and group delay responses of Thiran filters with delays of a fractional sampling period will be demonstrated. Thiran filters show favorable results for sample delay blocks with a temporal oversampling factor of three. Thiran fractional delays of orders three and four are mapped to Xilinx FPGA RF-SoC technologies for evaluation. The preliminary results of the APF-based Thiran fractional delays on FPGA can potentially be used to realize DVM factorizations using application-specific integrated circuit (ASIC) technology.
Article
Active phased-array systems are gaining popularity in many wireless applications due to their ability to electronically create, steer, and change multiple beams with high directivity as well as adaptively reduce external interference [1] . Fifth- and next-generation wireless communications are leveraging phased arrays to create smart base stations in sub-6-GHz Frequency Range 1 (FR1) [2] as well as overcoming the propagation losses in the Frequency Range 2 (FR2) millimeter-wave spectrum [3] . For space-based constellations like Starlink and Kuiper, ground stations utilize phased arrays to simultaneously track multiple satellites using different beams without any mechanical movement [4] . The stringent link budgets of radar applications have also benefited from the high directivity of phased arrays as well as their angle-of-arrival estimation accuracy without cumbersome and costly servo motors for object detection [5] . Finally, electronic warfare (EW) systems are beginning to leverage phased arrays to more accurately locate hostile signals in noisy environments and precisely direct their jamming attacks [6] .