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In this paper power and energy dissipation are reduced using transmission gate logic(TGL), which are the challenging factors in the VLSI CMOS design. In order to get strong output level PMOS and NMOS are connected together.In active mode, TGL technique achieves 83% power reduction as compared to the conventional CMOS design.125nm CMOS technology is...
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CMOS technology is mainly used in VLSI circuits to reduce the number of transistors and achieve the low power. We can reduce the power by using either circuit level optimization or logical level optimization. In this paper, the circuit level optimization process is followed to reduce the area and power. In the conventional technique, complementary...
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Citations
... It is an insulator with a bandgap of 5.3 eV. Sometimes hafnium is used as metal in high-pressure devices [13][14][15]. HfO2 is chemically inactive and is dissolvable in strong sulfuric acid and bases. At higher temperatures, the HfO2 reacts with chlorine to form Hafnium Tetrachloride or Graphite/Carbon Tetrachloride. ...
... The q is the electronic charge. Although InGaAs-based MOSFETs experience higher leakage current through the drain terminals [13,14], due to the gate scaling, the gate terminal has a slighter tunneling effect caused by the electrical field applied along with the gate terminal towards the drain terminal [15]. The new layer is proposed to reduce the increase of resistance due to the accessible gate terminal. ...
The Indium Gallium Arsenide (InGaAs) based MOSFETs have been widely used in the research of high-speed devices with higher frequency. It has some application in the designing areas of power amplifiers. The InGaAs mainly have greater electron mobility and the lesser band gap in their compound makes them more suitable for developing high-speed devices. The Indium Gallium Arsenide compound-based MOSFETs are designed using the source/drain grown on a passive layer of Indium Phosphide substrate. This helps in reducing the power budget of the MOSFET and thereby reduces source and drain resistance. The re-grown layers over the bulk have serious issues such as parasitic capacitance and greater electrical field at the terminals of the gate along with the drain terminal. This results in a larger leakage current along with the terminals and thereby induces the degradation of the frequency of the application amplifiers. The high-ƙ dielectric along the gate terminal makes the device immune to leakage current for lesser frequency applications. The optimum material for the dielectric may be Hafnium (IV) Oxide – HfO 2 which has been used as a sidewall in the proposed InGaAs MOSFET design. The device simulation was carried out in a way to evaluate the characteristics of the proposed designs. The results were submissive to the conventional MOSFETs in terms of output capacitance over the source and drain terminals, leakage current in the drain terminal, and improved frequency parameters. The results also suggested that the sidewall design over the gate terminal constitutes the frequency improvement without losing the power and current characteristics.
... In Fig. 7, the 3-bit binary encoder contains only 15 NMOS transistors and 6 memristors by using the new MRL, while the traditional CMOS technology requires at least 40 transistors for implementing the same encoder [1]. ...
... Similarly, the logical expressions of output signals Y 2 -Y 7 described by Eq. 14 can be obtained in the same way, such as Y 7 = X 2 ⋅X 1 +X 0 = X 2 X 1 X 0 . Compared with the traditional CMOS technology, which requires at least 70 transistors to construct a 3-bit binary decoder [1], only 20 NMOS transistors and 12 memristors are needed in this decoder circuit by using the new MRL modules. ...
... As shown in Fig. 16, the simulation results of the memristor-based 3-bit binary encoder are consistent with the corresponding truth table, which can realize the function of the encoder. Compared with CMOS-based 3-bit binary encoder [1], the designed memristor encoder consumes less power and uses less components and the results are shown in Table 2. At the same time, due to the use of less components, it can also be improved in reducing the area of chips. ...
This paper proposes three modified memristor ratioed logic (MRL) gates: NOT, NOR and A AND (NOR B) (i.e., A·B¯\documentclass[12pt]{minimal} \usepackage{amsmath} \usepackage{wasysym} \usepackage{amsfonts} \usepackage{amssymb} \usepackage{amsbsy} \usepackage{mathrsfs} \usepackage{upgreek} \setlength{\oddsidemargin}{-69pt} \begin{document}$$A \cdot \bar{B}$$\end{document}), each of which only needs 1 memristor and 1 NMOS. Based on the modified MRL gates, we design some combinational logic circuits, including 1-bit comparator, 3-bit binary encoder, 3-bit binary decoder and 4:1 multiplexer. Furthermore, an improved multifunctional logic module is proposed, which contains one NMOS transistor and five memristors, and can implement AND, OR and XOR logic operations. Using this multifunctional logic module, a 4-bit comparator and a 1-bit full adder are designed. Finally, the proposed combinational logic circuits are verified by LTSPICE simulations. Compared with other memristor-based logic circuits and the traditional CMOS technology, the proposed logic circuits have made great progress in reducing delay, power consumption and the number of transistors.
... Gate terminals are connected to each other via inverter. Logic circuits using transmission gate is compact than conventional gate and that is desirable for semiconductor industry [9]. ...
In this thesis project two alternate devices are used which stand out as replacements of MOSFETs. They are Carbon Nano Tube Field Effect Transistors (CNTFET) and Graphene Nano Ribbon Field Effect Transistor (GNRFET). Two different logics, conventional gate logic and transmission gate logic have been used for performance analysis. The performance analysis has been done on the basis of propagation delay and a 2:1 MUX circuit has been used in this purpose. Simulation work done by Hspice software.
... Though LB-CG has been beneficial in reducing power, its transistor count requires a filtering which has been possible by TG-CG. The TG-CG facilitates the reduction in transistor count by 21.43%; but gives a penalty in average power in comparison to LB-CG as TG fails to block the static current [29][30]. However, the transistor count is reduced by 53.57% in PTL-CG. ...
Advancement in technology towards mobile computing and communication demands longer battery life, which mandates the low power design methodologies. In this paper, we have presented a novel low power 8T flip-flop (FF) architecture, which has outsmarted the existing well known dynamic, semi-dynamic and explicit pulsed Flip-flops in terms of power and delay. The major ingredient of this architecture is a voltage keeper, which is incorporated to achieve reliable logic switching at the propagating nodes of the design. However, we have also come up with two new approaches of gated clock generation based on Transmission Gate (TG) & Pass Transistor Logic (PTL) as a modification of LECTOR based gating. These gating logics have proved themselves to be competent enough to reduce both the static and dynamic power dissipation and hence are employed to the proposed Flip-flop to achieve further reduction in power than its non–gated correspondent. The performance of this proposed Gated Flip-Flop is tested in a Finite State Machine with its application in low power serial adder design. All the simulations are carried out using 65nm and 90nm CMOS technology with a power supply of 1.1Volt at 6.6GHz clock frequency. The Gated FF saves 52.12%, 6.36% and 28.18% average power using LECTOR, TG & PTL respectively with respect to its non-gated counterpart in 65nm technology. The performance metrics of gated and non-gated proposed designs are affirmed in the environment of commercialized CMOS foundry.
... To detect the vehicle number plate region in an image [8] discussed two techniques, boundary feature and color feature to possess better performance than single feature technique. The algorithm for number plate localization especially for Indian vehicles, [9] proposed a simple and good performance algorithm which uses Top Hat Transformation. ...
Day by day the use of vehicles in our life is rising exponentially and as increasing vehicles are violating the rules of traffic, theft of vehicles, ingoing to restricted areas, abnormal number of accidents lead to upturn in the crime rates linearly. For any vehicle to be acknowledged, vehicle license plate detection will play a main significant job in this active world. The commonly used in field of safetyand security system, LPDR plays a significant role and we need to identify vehicles registration number at anevident distance for finding the vehicle.The methodology which we have used is modest but appropriate. First the segmented of all characters in the image (Licence Plate). Ultimately, the recognition of each character is done. The pattern matching method is used for recognition each character in the vehicle license plate.
