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Context 1
... the end of simulation, the design was fully validated and the performance detail is printed in console in a review report which is presented in Fig. 3. ...
Context 2
... the proposed methodology presented no problems to completely verify the AES encryption module reaching all objectives defined in the verification plan. Second, the elapse time of simulation was 112.54 seconds (Shown in Fig. 3) and it did not saturate the RAM of the computer which validates this unit-level verification to be employed in any system-level verification. Finally, the modular structure developed a direct interaction with the DUV only in the lower layer which means that it is reusable with any other AES encryption module design or with another bus ...
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Citations
... Functional coverage The functional coverage analysis review of the DUV is presented in Fig. 5. First, the Code Coverage goals and Functional Coverage goals defined in the verification plan were achieved, and there were no errors encountered. This is correct considering that the DUV had been previously verified by the designer with a directed test verification, by two different SystemVerilog-Based verification tests in [8] and [9], and it is an IP core allocated on the OpenCores online repository. ...
... Second, the performance held by the verification process presented higher metrics of code coverage in comparison with [8] and [9], which is summarized in TABLE IX. Both works in [8] and [9] are SystemVerilog-Based Functional verification tests and analyze the same DUV. ...
... Second, the performance held by the verification process presented higher metrics of code coverage in comparison with [8] and [9], which is summarized in TABLE IX. Both works in [8] and [9] are SystemVerilog-Based Functional verification tests and analyze the same DUV. Besides, in contrast of the work in [8] which presented no results of functional coverage, the present work as well as the work in [9] reach 100% in all coverpoints and assertions as shown previously. ...
