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(Fig. 1a) The changing of a chromosome using the mutation operator [6]. (Fig. 1b) The changing of a chromosome using the single point recombination operator [6].
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Technology mapping is the transformation of a general Boolean logic network into a functional equivalent K-LUT network that can be implemented by the target FPGA device. Because an FPGA architecture is pre-determined, technology mapping is limited to the available resources. However, circuits can be optimized before the low-level synthesis phase. O...
Citations
... Therefore, in this newly developed Yosys+Odin flow, Yosys provides better language coverage support and performs HDL elaboration followed by coarse-grained optimizations. After that, Odin II performs partial technology mapping based on the target FPGA architecture using a mix of genetic algorithms [49] and tradeoff analysis of hard vs. soft logic inference [50], and then writes out the final netlist as illustrated in Fig. 3. ...
With the prevalence of deep learning (DL) in many applications, researchers are investigating different ways of optimizing FPGA architecture and CAD to achieve better quality-of-results (QoR) on DL-based workloads. In this optimization process, benchmark circuits are an essential component; the QoR achieved on a set of benchmarks is the main driver for architecture and CAD design choices. However, current academic benchmark suites are inadequate, as they do not capture any designs from the DL domain. This work presents the second version of our suite of DL acceleration benchmark circuits for FPGA architecture and CAD research, called Koios. This suite of 40 circuits covers a wide variety of accelerated neural networks, design sizes, implementation styles, abstraction levels, and numerical precisions. These benchmarks include 32 DL designs and 8 synthetic (proxy) benchmarks. The Koios benchmarks are larger, more data parallel, more heterogeneous, more deeply pipelined, and utilize more FPGA architectural features compared to existing open-source benchmarks. This enables researchers to pinpoint architectural inefficiencies for this class of workloads and optimize CAD tools on more representative benchmarks that stress the CAD algorithms in different ways. In this paper, we describe the Koios designs, compare their characteristics to prior FPGA benchmark suites, and present results of running them through the Verilog-to-Routing (VTR) flow using a recent FPGA architecture model. Finally, we present case studies showing how exploration of DL-optimized FPGA architecture and CAD algorithms can be performed using our new benchmark suite.
... Genetic algorithms (GA) are renowned for their ability to find exceptional solutions for a variety of applications. ODIN II is composed of six processes namely: parsing, AST optimization, netlist elaboration, netlist technology mapping, netlist optimization, and Berkeley Logic Interchange Format (BLIF) file generation [2]. ODIN II parses the Verilog HDL code into an AST [6] and optimizes it in the first and second steps. ...
... The final phase transforms the AST into a netlist representation of the circuit at a high level. ODIN II's decomposition of high-level logic into primitives impedes GA's ability to determine whether the type of a particular soft logic is suitable for the design objective [2]. ODIN II partial mapper takes advantages of GA in the adder mapping phase. ...
... Although Odin-II currently suffers from the lack of full Verilog language coverage support, its strength is in providing a complex partial mapping [2]. Odin-II can perform hard logic inference for available blocks in FPGA architectures, generate the desired device footprint using a genetic algorithm in the soft logic instantiation [3], and provide hard/soft logic tradeoff decisions that can be initialized before partial mapping [4]. ...
... Damghani et al. [27] demonstrated that using a genetic algorithm during synthesis can improve soft logic circuit generation. It discussed changes to the partial mapping logic of ODIN II for some modules when there are no hard blocks available. ...
