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Now a days, an efficient arithmetic operations are important to accomplish the high performance. In every one of these applications, multiplier is an important arithmetic operation. Usually multipliers are utilized to evaluate the square operand. A square operation is faster than a multiplication. This paper proposes a high performance and area eff...
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... This gate has 5 input variables, (A, B, C, D, E), and its output vector is (P, Q, R, S, T). Figure 3 shows the implementation block of the BVPPG gate. It has the quantum cost of 5 [20][21][22]. ...
The paper proposes a novel 3 × 3 reversible gate which has varied functionality for logical and arithmetic operations. The advancements in VLSI demand higher operational speed and less time delay, which leads to increased complexity and more power dissipation in the design. The continuous evolution of DSP applications demands improvisation on the multiplier design that is faster and more power efficient. Reversible logic is an efficient solution to the above problems. In the paper, a basic 2 × 2 multiplier, the proposed novel gate, and its enhanced capability for implementing half adder-subtractor over existing basic reversible gates are discussed. The proposed designs were implemented on QCA Designer.
There is a rapid growth in semiconductor technology as the need for digital application systems has increased. Arithmetic operations such as addition and multiplication play a major role in DSP applications. As a result, there is thorough research on various methods to achieve high-speed and low-power DSP applications. In multipliers, the Vedic multiplier is considered as a fast multiplier because of its consistent structure resulting in low power consumption. Array multiplier is implemented with half and full adders. This kind of implementation of the array multiplier needs the previous output to provide the last word output, which leads to an increase in delay. In DSP applications, the key problem corresponds to carry generation delay. To overcome the delay, a carry-lookahead adder is used. In this work, a Vedic multiplier using a carry-lookahead adder is used with quaternary logic in the CMOS process. The width and length of the transistors are defined as 1.7 µm (PMOS), 850 nm (NMOS), and 180 nm for 1.8 V supply in 180 nm CMOS process. Simulation results show that the designed Vedic multiplier enhances the performance when compared with the conventional multiplier.
This paper is regarding the design and analysis of an efficient 8×8 Vedic multiplier by the principle of Vedic mathematics [1]. Here, a unique Vedic multiplier architecture is adapted, which is not based on the regular method of multiplication (addition, shifting). The design is as per the "Urdhwa-Tiryakbhyam Sutra" of Vedic mathematics. Two numbers (binary of 8-bit each) are multiplied using the methodology of this principle/sutra. "Urdhwa-Tiryakbhyam" means "vertically and crosswise", wherein the partial products are computed at once, thus lessening the delay and hence making the multiplication faster. This 8 by 8 bit multiplier is coded in Verilog HDL and tested on a DE10-lite FPGA kit.
Constructing a binary tree, the Huffman algorithm introduced the method of text compression that helps to reduce the size keeping the original message of the file. Nowadays, Huffman-based algorithm assessment can be measured in two ways; one in terms of space, another is decoding speed. The requirement of memory for a text file is going to be reasonable while the time effectiveness of Huffman decoding is being more significant. Meanwhile, this research is introducing the adjacent distance array with Huffman principle as a new data structure for encoding, and decoding the Bengali text compression using transliterated English text. Since the transliterated English text accommodates to reduce the unit of symbols accordingly, we transliterated the Bengali text into English and then applied the Huffman principle with adjacent distance array. By calculating the ASCII values, adjacent distance array is used to save the distances for each adjacent symbols. Apart from the regular Huffman algorithm, a codeword has produced by traversing the whole Huffman tree for a character in case, respectively adopting the threshold value and adjacent distance array can skip the lengthy codeword and perform the decoding manner to decode estimating the distances for all adjacent symbols except traversing the whole tree. Our findings have acquired 27.54% and 20.94% compression ratios for some specimen transliterated Bengali texts, as well as accomplished a significant ratio on different corpora.
Topological index is the molecular-graph-based structure descriptors. Computational chemistry is a discipline in which we use mathematical approaches for the computation and simulation of molecular behaviour or properties. Detour index is one of the topological index in the collected works of computational chemistry. In this article the authors have computed detour index of join of certain graphs.
