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Exponential spatial correlation function and spatial correlation matrix contour plots at correlation distance of rc = 100 µm and different chip area and resolutions.
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A recent study shows that the existing first-order canonical timing model is not sufficient to represent the dependency of the gate/wire delay on the processing and operational variations when these variations become more and more significant. Due to nonlinear mapping from variation sources to the gate/wire delay, the distribution of the delay will...
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... a global parameter G, as illustrated in Fig. 5(a), the covariance between the global variations at positions i and j will have the following ...
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... shown in Fig. 5, the covariance matrix will always have a "band" structure where the number of bands in the matrix is decided by the user-defined parameter resolution, i.e., the higher the resolution is, the more bands there are and the less sparse the matrix is [ Fig. 5(b) and (c)]. With the same resolution, the number of bands will be the same as ...
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... shown in Fig. 5, the covariance matrix will always have a "band" structure where the number of bands in the matrix is decided by the user-defined parameter resolution, i.e., the higher the resolution is, the more bands there are and the less sparse the matrix is [ Fig. 5(b) and (c)]. With the same resolution, the number of bands will be the same as shown in ...
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... a circuit with N gates, there are t types of global variation sources and that there are, in total, q global variation variables considering spatial correlation. Both covari- ance matrix Σ and quadratic coefficient matrix Γ are sparse matrices. The number of nonzero elements in Γ will be O(t 2 ). Matrix Σ will have a "band" structure as shown in Fig. 5 and will have O(q) significant nonzero elements. Because the types of global variation sources are usually very limited for a particular technology, i.e., q t, the additional computation needed to switching from the first-order timing model to the quadratic timing model will be mainly contributed from the moment evaluation equations ...
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Citations
... Statistical Static Timing Analysis (SSTA) is a widely used method for timing analysis in digital circuits in the presence of process variations. There are many SSTA methods that trades off between time complexity and accuracy [6][7][8][9][10][11]. Statistical timing optimization methods take advantages of SSTAs as the basis in order to improve the performance/yield of a digital circuit considering the impacts of process variations [12]. ...
As CMOS devices become smaller, process variations-induced uncertainty imposes a large spread in the circuit timing and therefore, it becomes one of the main issues for circuit yield. To analyse/optimise the timing of the circuit under process variation effects, statistical analysis/optimisation techniques are more suitable than the traditional static analysis/optimisation counterparts. Statistical gate sizing is an effective technique that is widely used to guide the timing yield improvement of digital circuits. Gate criticality, defined as the probability that a gate lies on a critical path, forms the basis for many of the existing statistical gate sizing techniques. Here, the authors introduce adjacency criticality to address the drawbacks of the conventional definition of gate criticality. It is defined as the probability of manufacturing a chip in which the gate lies on the critical path due to process variation considering the effect of the gates in its fan-out cone. Furthermore, the authors present the levelised Adjacency Criticality metric which provides a trade-off between the runtime of the criticality metric and accuracy of the Adjacency Criticality metric. In order to show the efficacy of the proposed metric, an adjacency criticality-based statistical gate sizing method is presented for improving timing yield of the circuit.
... New methods for handling reconvergence and spatial correlations have been proposed in block-based SSTA, for example [4], [5]. In most of these approaches, there is a focus on the correct computation of the statistical maximum, taking proper correlation into consideration. ...
The increasing process variations which goes along with the continuing CMOS technology shrinking necessitate accurate statistical timing analysis. Multiple Input Simultaneous Switching (MISS) is simplified to Single Input Switching (SIS) in most of the recent approaches, which introduces significant errors in Statistical Static Timing Analysis (SSTA). Hence, we propose a new modeling and statistical analysis method to capture statistical gate delay variations, able to accurately handle MISS. Experiment results obtained with a 45 nm technology show that our approach accurately obtains not only mean and standard deviation, but also the third moment, skewness.
This paper focuses on statistical optimization and, more specifically, timing yield (TY)-constrained optimization. For cell replacement in timing-constrained optimization, we need an indicator that examines whether or not a timing violation occurs and gives the available timing for a gate. In deterministic optimization, the timing slack is used for this indicator. Although there is an analogous concept of TY slack in statistical optimization, it has not been well utilized. This paper proposes an effective way to use the TY slack for successful statistical optimization. To achieve this, we present an efficient method to calculate the TY slacks of gates and a strategy that uses timing resources for effective statistical optimization. Based on this work, we propose a novel statistical leakage minimization method that uses the TY slack for a gate change metric. The use of TY-based metrics that are appropriate for statistical design ensures that our method has a better optimization performance at a higher speed. Experimental results on ISCAS-85 benchmark circuits show that the leakage minimization method reduces leakage by 25.2% compared to the statistical benchmark method. In addition, our method has a better runtime when the number of gates is high.
As the device geometries are shrinking, the impact of crosstalk effects increases, which results in a stronger dependence of interconnect delay on the input arrival time difference between victim and aggressor inputs (input skew). The increasing process variations lead to statistical input skew which induces significant interconnect delay variations. Therefore, it is necessary to take input skew variation into account for interconnect delay calculation in the presence of process variations. Existing timing analysis tools evaluate gate and interconnect delays separately. In this paper, we focus on statistical interconnect delay calculation considering crosstalk effects. A piecewise linear delay-change-curve model enables closed-form analytical evaluation of the statistical interconnect delay caused by input skew (SK) variations. This method can handle arbitrarily distributed SK variations. The process-variation (PV)-induced interconnect delay variation is handled in a quadratic delay model which considers coupling effects. The SK- and PV-induced interconnect delay variations are combined together for crosstalk-aware statistical interconnect delay calculation. The experimental results indicate that the proposed method can predict the interconnect delay impacted by both input skew variation and process variations with average (maximum) absolute mean error 0.25% (0.75%) and standard deviation error 1.31% (3.53%) for different types of coupled wires in a 65nm technology.
As CMOS technology scales, to consider process variation becomes increasingly challenging. Statistical gate delay model is widely used technique to analyze the influence of process variation on gate delay. We propose a second-order gate delay model which is more accurate even with the larger variance of variations. The number of additional variables introduced by second-order terms is minimized using sensitivities and statistically combined variables. The runtime cost to calculate sensitivity values is reduced by simplifying the process to determine worst-case and best-case parameters. The accuracy of the model is verified by experiments on a gate, inverter-chain, and a circuit. Comparing to Monte Carlo simulation, the mean and standard deviation obtained by the proposed model have average error rates of 1.26% and 4.31%, respectively. We present the error reduction rate of the proposed model, compared to the first-order model. The average error reduction rate is 36.7%.
In deterministic timing optimization, timing slack is used to verify whether a timing violation occurs or not without timing updates on the entire circuit. However, in statistical timing optimization, there is currently no criterion to verify whether a timing violation occurs. This paper proposes a novel metric of timing yield slack to verify whether the timing yield violation occurs without updating the timing yield of the entire circuit. This paper also presents an efficient method to compute the proposed timing yield slacks of gates and a strategy to use timing resources for effective statistical optimization. Experimental results on ISCAS-85 benchmark circuits showed that the proposed timing yield slack calculation method has only a 1.89% error on average, and improves the runtime by 460 times as compared with the exact calculation method. Also, the proposed method has a small runtime overhead of 4.85% against the statistical static timing analysis.
This paper presents a novel method for full-chip statistical leakage estimation that considers the impact of process variation. The proposed method considers the correlations among leakage currents in a chip and the state dependence of the leakage current of a cell for an accurate analysis. For an efficient addition of the cell leakage currents, we propose the virtual-cell approximation (VCA), which sums cell leakage currents sequentially by approximating their sum as the leakage current of a single virtual cell while preserving the correlations among leakage currents. By the use of the VCA, the proposed method efficiently calculates a full-chip leakage current. Experimental results using ISCAS benchmarks at various process variation levels showed that the proposed method provides an accurate result by demonstrating average leakage mean and standard deviation errors of 3.12% and 2.22%, respectively, when compared with the results of a Monte Carlo (MC) simulation-based leakage estimation. In efficiency, the proposed method also demonstrated to be 5000 times faster than MC simulation-based leakage estimations and 9000 times faster than the Wilkinson's method-based leakage estimation.
Incremental analysis is indispensible for efficient circuit optimization, as it analyzes the effect by the modified circuit part only instead of analyzing a whole circuit again from beginning. This paper presents a new incremental statistical static timing analysis (SSTA) method, called timing yield-based incremental analysis (TYIA). TYIA uses the probability that the gate timing slack is non-negative to prune the timing change propagation after a gate replacement. In the experimental results using ISCAS-85 benchmarks, TYIA showed 2~5 times better accuracy in timing yield analysis at comparable efficiency, when compared to the existing incremental SSTA methods.
While first-order statistical static timing analysis (SSTA) techniques enjoy good runtime efficiency desired for tackling large industrial designs, more accurate second-order SSTA techniques have been proposed to improve the analysis accuracy, but at the cost of high computational complexity. Although many sources of variations may impact the circuit performance, considering a large number of inter- and intra-die variations in the traditional SSTA is very challenging. In this paper, we address the analysis complexity brought by high parameter dimensionality in SSTA and propose an accurate yet fast second-order SSTA algorithm based on novel on-the-fly parameter dimension reduction techniques. By developing a reduced rank regression (RRR)-based approach and a method of moments (MOM)-based parameter reduction algorithm within the block-based SSTA flow, we demonstrate that accurate second-order SSTA can be extended to a much higher parameter dimensionality than what is possible before. Our experimental results have shown that the proposed parameter reductions can achieve up to 10times parameter dimension reduction and lead to significantly improved second-order SSTA under a large set of process variations.
