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Exponential rise/decay assumptions fit actual noise waveform better than simpler linear rise/exponential decay.
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A novel concept of bidirectional transformation between on-chip coupling noise waveform and delay-change curve (DCC) using closed-form equations is described in this paper. These equations are targeted for use in: 1) the efficient generation of DCCs and 2) accurate experimental determination of subnanosecond coupling noise. In particular, we explor...
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Citations
... By modeling the receiver as load capacitance CL and the driver as a ramp voltage source with impedance RS and transition time tr [27], the interconnect coupling system can be approximated as a linear passive network. The bus output signal can be ob-tained by superimposing the injected noise onto its nominal response [28,29]. Due to the shielding effect, the noise injected by adjacent buses is mainly considered. ...
High-bandwidth interconnects between chiplets employ parallel interfaces, whose performance is limited by inter-channel crosstalk. In order to reduce the delay uncertainty (jitter) induced by crosstalk, this work analyzes the effect of signal skew and proposes a static skew scheme and a novel dynamic skew scheme. A fast algorithm is also suggested to determine the optimal skew value for the dynamic scheme. The experiment results show that the static scheme can significantly reduce jitter for low-speed buses but fails at high speed. By contrast, the dynamic scheme reduces jitter by about 44% for low-speed buses, reduces the jitter increment due to intersymbol interference by about 71%, and is effective at a higher bus rate. The proposed signal skew schemes require no additional routing overhead.
... Considering crosstalk-induced delay will improve the accuracy in static timing analysis. Several methods [21]–[23] have been proposed to calculate the impact of crosstalk on interconnect delay. Any of these delay calculation methods could be used in our approach. ...
As the feature size scales down, crosstalk noise on circuit timing becomes increasingly significant. In this paper, we propose a path delay test generation method toward activa- tion of worst case crosstalk effects, in order to decrease the test escape of delay testing. The proposed method performs tran- sition-map-based timing analysis to identify crosstalk-sensitive critical paths, followed by a deterministic test generation process. Using the transition map instead of the timing window to manage the timing information, the proposed method can identify many false coupling sites and thus reduce the pessimism in crosstalk-in- duced fault collection caused by inaccurate timing analysis. It can also efficiently calculate the accumulative crosstalk-induced delay, and find the sub-paths which cause worst case crosstalk effects during test generation. By converting the timing constraints of coupling lines into logic constraints, complex timing processing for crosstalk effect activation is avoided during test generation. In addition, the tradeoff between accuracy and efficiency can be explored by varying the size of timescale used in the transition map.
... Even a small noise can cause an error if the victim net is on a critical path. The timing information of both the aggressor and victim paths is required to correctly analyze the effect of delay change [46]. Accordingly, delay-change analysis has to be much more comprehensive than the verification of the noise peak and tightly coupled with timing analysis. ...
Variability, reliability, and design size are becoming major difficulties in system-on-a-chip (SoC) designs as the scaling of semiconductor technology advances. Techniques for interconnect modeling and analysis in designing advanced SoCs are discussed from the design-automation point of view. Importance of interconnect modeling in modern chip-design flows is first summarized. State-of-the-art physical-design techniques for parasitic extraction, signal-integrity analysis, and timing analysis (which are commonly executed throughout the final verification of physical design) are then reviewed. The extraction and analysis require the most accurate process information and modeling. Requests with respect to the manufacturing-design interface are discussed, and the authors' perspective concerning future SoC physical designs is addressed with emphasis on interactions between manufacturing and design technologies.
... Kahng et al. (2000) argue that MFs 3 and –1 corresponding to worst-case and best-case delay scenarios may not be correct upper and lower bounds for exponential type waveforms. As the coupling capacitor sees exponential waveforms rather than ramp waveforms on its terminals, the aggressor and victim waveforms should be represented by exponential functions rather than saturated ramp functions (Kahng et al. 2000; Agarwal et al. 2002; Sato et al. 2003). However, correct MF values corresponding to exponential cases were never shown to our knowledge. ...
The increase in interconnect delay due to coupling can have a dramatic effect on the circuit performance for nanoscale technologies. Calculation of coupling-induced delay using a traditional circuit simulator is computationally inefficient, and hence alternative prediction models are desirable. In this work, we revisit Miller factor (MF) based methodology for realistic exponential waveforms for the very first time. It was previously argued that for exponential inputs, the MFs could be more than 3 for worst case and less than 71 for best-case delay estimation. We have found the correct MFs corresponding to the worst case and best-case scenarios under exponential inputs and formulated for the partial overlapping case. Simulation results are shown for both worst-case and the best-case MFs and results are compared with the coupled RC network for 50% delay. We obtained an average error of 2.7% on worst-case and 3.3% on best-case delay using the MF derived for exponential waveforms. This model is useful as a quick reference in verifying a large number of nets for delay estimation.
... The previous methods concentrate mostly on saturated ramp or step inputs for aggressors. It has been argued in678 that active aggressors are more closely approximated by exponential waveforms. Therefore, an exponential type aggressor waveform has been utilized in the derivations. ...
This work proposes an accurate crosstalk noise estimation method in the presence of multiple RC lines for use in design automation tools. The method correctly models the loading effects of non switching aggressors and aggressor tree branches using resistive shielding effect and realistic exponential input waveform. Noise peak and width expressions derived show very good results in comparison to HSPICE results. Results show that average error for noise peak is 4.1% and for the width is 6.8% while allowing for very fast analysis.
... Such noise is quantified by peak noise voltage [ 3]. If noise is injected on the victim net during logic transition, it can modify the victim's waveform, causing delay uncertainty (Fig 1b) [ 4,5,6]. As a result, net delay becomes unpredictable and a non-critical path can become critical. ...
Capacitive coupling is the primary source of noise in nanometer technology digital CMOS VLSI circuits. It becomes worse with technology scaling. The interconnect capacitive crosstalk noise can be characterized by two parameters: peak noise voltage, and delay uncertainty. Delay uncertainty optimization can be seen as a subset of interconnect delay optimization. This paper addresses the problem of ordering and sizing parallel wires in a single metal layer within an interconnect channel of a given width, such that cross-capacitances are optimally shared for simultaneous noise and delay minimization. Using an Elmore delay model including cross capacitances for a bundle of wires and well-known crosstalk models, we show that "symmetric hill" wire ordering according to the strength of signal drivers, which is known to optimize channel timing characteristics, can be used also for minimizing channel noise metrics. Examples using state-of-the-art circuits in 65-nanometer technology are analyzed and discussed.
... Typically, dynamic delay is modeled by replacing the coupling capacitance between two wires by an equivalent ground capacitance based on the Miller effect [15]. A few other approaches model dynamic delay by the superposition of a static-noise waveform on the nominal switching waveform of the isolated victim [16], [17]. These superposition-based approaches require accurate modeling of static noise and nominal victim waveforms. ...
... Dynamic delay can be modeled by the superposition of the static-noise waveform on the isolated victim waveform. In [33], and subsequently in [16], previous authors have used this principle to describe dynamic delay. In [16], static noise is approximated by a linear ramp followed by a decaying exponential term. ...
... In [33], and subsequently in [16], previous authors have used this principle to describe dynamic delay. In [16], static noise is approximated by a linear ramp followed by a decaying exponential term. The isolated victim waveform is modeled as an exponential function. ...
In this paper, statistical models for the efficient analysis of interconnect delay and crosstalk noise in the presence of back-end process variations are developed. The proposed models enable closed-form computation of means and variances of interconnect-delay, crosstalk-noise peak, and coupling-induced-delay change for given magnitudes of variation in relevant process parameters, such as linewidth, metal thickness, metal spacing, and interlayer dielectric (ILD) thickness. The proposed approach is based on the observation that if the variations in different physical dimensions are assumed to be independent normal random variables, then the interconnect behavior also tends to have a Gaussian distribution. In the proposed statistical models, delay and noise are expressed directly as functions of changes in physical parameters. This formulation allows us to preserve all correlations and can be very useful in evaluating delay and noise sensitivities due to changes in various physical dimensions. For interconnect-delay computation, the authors express the resistance and capacitance of a line as a linear function of random variables and then use these to compute circuit moments. They show that ignoring higher order terms in the resulting variational moments does not result in a loss of accuracy. Finally, these variability-aware moments are used in known closed-form delay and slew metrics to compute interconnect-delay probability density functions (pdfs). Similarly for coupling noise and dynamic-delay analysis, the authors rely on the linearity (Gaussian) assumption, allowing us to truncate nonlinear terms and express noise and dynamic-delay pdfs as linear functions of variations in relevant geometric dimensions. They compare their approach to SPICE-based Monte Carlo simulations and report the error in mean and standard deviation of interconnect delay to be 1% and 4% on average, respectively
... Signals may also arrive at different phases due to unbalanced signal paths, or because of deliberate timing intervals to reduce crosstalk noise or peak current draw [2]. The relative input timing of aggressor and victim nets influences strongly the coupling noise on a victim net [3], [4]. ...
... Although copper/low κ materials have been introduced for deep-submicrometer (DSM) interconnects, it may become insufficient as technology goes below 100 nm. Recent studies have shown that the traditional hardwired metal interconnect systems will eventually encounter fundamental limits and may impede the advances of future ultralarge-scale integrated systems (ULSIs) [3]. As a result, alternative interconnect concepts such as radio frequency (RF)/microwave are identified as possible resolutions to global interconnect issues [15]. ...
... Recent advances in silicon integrated circuit technology are making possible tiny low-cost antennae, receivers, and transmitters to be integrated onto a single chip. As a result, a new RF/microwave interconnect technology has been introduced for future intrachip communication [3], [9]. Using the ROC technology, chip-based wireless radios can replace the wires to increase accessibility, to improve bandwidth utilization, and to eliminate delay and crosstalk noise in conventional wired interconnects. ...
In this paper, an analytical model to estimate crosstalk noise and intersymbol interference on capacitively and inductively coupled point-to-point on-chip buses is derived. The derived closed-form equation for output voltage enables the usage of the model in computer-aided design (CAD) tools for complex systems where high simulation speed is essential. The model also combines together properties such as inductive coupling, initial conditions, signal rise time, input phases, and bit sequences that have not been included in a single closed-form model before. The model is compared to HSPICE and previous models. The model and HSPICE are in good agreement with each other
... Given the statistical characteristics of the signal arrival times, a Monte-Carlo based enumeration method can be applied to obtain the statistical behavior of delay through coupled interconnects. The methods of deriving the delay change curves for a given coupled interconnect consists of SPICE-based methods [7], [8], and analytical methods [9], [10]. The quality of DCC directly impacts the overall accuracy but also incurs high computational cost. ...
... This paper proposes a sensitivity based analytical approach to further reduce the computational cost while a slightly better accuracy than the existing analytical approaches. This paper has been organized as follows: Section II, we briefly discuss the existing approaches used to generate delay change characteristics [7], [8], [9], [10] and predict its statistics [6]. In Section III, we will develop a model to express the delay changes using analytical equations that speeds up the process of statistical prediction. ...
... The model has been characterized as an exponential function of RSAT for the rise part of the curve (Left part), and as a linear function of the RSAT for the fall part of the curve (Right part). This is used since the delay change curve is characterized as an exponential + linear model [10], and the MCF curve is obtained by scaling the dcc using the relationship seen in Equation 1. A smoothing function was implemented around the peak MCF value. ...
Performance optimization is a critical step in the design of integrated circuits. Rapid advances in very large scale integration (VLSI) technology have enabled shrinking feature sizes, wire widths, and wire spacings, making the effects of coupling capacitance more apparent. As signals switch faster, noise due to coupling between neighboring wires becomes more pronounced. Changing the relative signal arrival times (RSATs) alters the victim line delay due to the varying coupling noise on the victim line. The authors propose a sensitivity-based method to analyze delay uncertainties of coupled interconnects due to uncertain signal arrival times at its inputs. Compared to existing methods of analyzing delay uncertainties of coupled interconnects, the simulation results show that the proposed method strikes a good balance between model accuracy and complexity compared to the existing approaches.
... We think an alternative is to use an exponential rise and exponential decay approximation to describe the crosstalk noise. Dual-exponential crosstalk noise metrics are also a requirement in some researches, such as [7] [8]. In this paper based on dual-exponential approximation we obtain our crosstalk noise metrics including V p , Tp and Wn at one time with acceptable accuracy. ...
... Up to now we get two S-domain expressions for victim output V 2 , one is ) ( ' 2 s V in (12), and the other one is V 2 (s) in (8). Let's set ) ( ' 2 s V equal to V 2 (s), and match their corresponding moments: ...
... Here f i (i=1, 2, 3) can be gotten from (8). Solving (17) Figure 2. Three different crosstalk noise Waveform approximations (14). ...
Based on the assumption that crosstalk noise is dual-exponential waveform, in this paper we present the closed-form crosstalk noise metrics including the peak noise amplitude V<sub>p</sub>, peak noise occurring time T<sub>p</sub> and pulse width W<sub>n</sub>. Then using part of our metrics we study aggressors switching times alignment that leads to worst-case crosstalk noise for a quiet victim from the analysis of peak noise window (PNW). The SPICE simulation results confirm the accuracy of our metrics and our analysis.
