Figure 4 - uploaded by Sorin A. Huss
Content may be subject to copyright.
Source publication
This paper presents a methodology for calculating highly accurate mean power estimates for integrated digital CMOS circuits. A complementary calibration scheme for ASIC library cells to extract the power relevant parameters is proposed. The circuit models presented allows the prediction of mean power dissipation of gate-level designs in CMOS techno...
Context in source publication
Similar publications
![Fig. 1. VLSI System Design Model [4]](profile/Pawan-Dahiya/publication/280557997/figure/fig1/AS:669515268513800@1536636287741/VLSI-System-Design-Model-4_Q320.jpg)
VLSI design has moved from an exotic, expensive curiosity to everyday necessity. The designers have refocused their concentration away from circuit design and towards advanced logic and system design. Minimizing inter-connection length has long been a prevailing objective in VLSI routing. It leads to delays which may affect performance of any integ...
![Fig. 1. Relationship between V and delay of a CMOS VLSI device [8].](profile/Tughrul-Arslan/publication/3418615/figure/fig1/AS:394705851437056@1471116616254/Relationship-between-V-and-delay-of-a-CMOS-VLSI-device-8_Q320.jpg)
This paper presents a new tool for the synthesis of low-power VLSI
designs, specifically, those designs targeting digital signal processing
applications. The synthesis tool genetic algorithm for low-power
synthesis (GALOPS) uses a genetic algorithm to apply power-reducing
transformations to high-level signal-processing designs, producing
designs th...
This work studies the problem of CMOS operational amplifiers
(OpAmps) design optimisation. The synthesis of these amplifiers can be
translated into a multiple-objective optimisation task, in which a large
number of specifications have to be taken into account, i.e., GBW area,
power consumption and others. We introduce and apply the genetic
algorith...
In this paper, a new clock tree distribution design flow and algorithm of clock gates splitting to improve the clock tree power dissipation had been presented. The clock gating components are inserted in clock tree during VLSI design flow to reduce clock tree dynamic power consumption. The effective splitting and physical placement of the clock gat...
Introducing redundancy at the device-level has been proposed as the most effective way to improve reliability. With the remarkable reliability of the complementary metal oxide semiconductor (CMOS) transistors the semiconductor industry was able to fabricate, the research on device-level redundancy has reduced. However, the increasing sensitivity to...
Citations
... Ref.[5] records input and output signal switching information and explains the power dissipation and coefficients relationship by recursive least square algorithm. In Ref.[6], Bachmann studied the power estimation method based on event-driven simulation , and discuss simulation algorithms. Hsieh proposed build power model for sequential circuits using neural networks [7] , but that method only considered the transition of circuit's port signals. ...
Bayesian modeling method and slice anal-ysis techniques show good effect in cycle-accurate power analysis of combinational circuit. In this paper, we use vir-tual signal logical depth assignment to resolve the problem that signal loop can not be sliced in sequential circuits. With this method, we build cycle-accurate power model based on Bayesian inference and slice analysis techniques. The experiments on ISCAS89 benchmark show that the power-per-cycle estimation error is 6.7%. By analyzing the relation between error trend under different slices and cir-cuit's size, we also build a thumb rule about how to choose best slice number: when the accumulative gate number is about 73% of total gate number, the model error with slice-based parameters usually arrives minimum value.
... Wireless sensor networks operating on limited energy resources [2] need to be power efficient to extend system lifetime and reduce maintenance costs with fewer battery replacements. This has to happen at each level of design abstraction, from circuit level [3] up to software and network levels [4], especially for video networks as image sensors (cameras) tend to have much higher power consumption rates compared to other sensors. This work focuses on the problem of coordinated power management (PM) for video sensor networks working at the application level. ...
Wireless sensor networks operating on limited energy resources need to be power efficient to extend the system lifetime. This is especially challenging for video sensor networks due to the large volumes of data they need to process in short periods of time. Towards this end, this paper proposes two coordinated power management policies for video sensor networks. These policies are scalable as the system grows and flexible to video parameters and network characteristics. In addition to simulation results, the prototype demonstrates the feasibility of implementing these policies. Finally, the analytical framework we provide gives an upper bound for the achievable sleep fraction and insight into how adjusting select parameters will affect the performance of the power management policies
Exponential increase in scale of integration, is increasing day by day and movement of high volume information among various parts of computing system contributes a lot on overall power budget. Feasibility of system depends on power consumption in modern computing systems. There are various ways to reduce power requirement. Dynamic power requirement is the dominating factor among them. Power consumption due to communication on system-level buses contributes a lot of power consumption. Scheme used to reduce dynamic power in called as bus encoding technique. Various schemes have been proposed in literature to encode data to reduce the number of bus transition. Data volume of information that belongs to computer system is not always used with equal probability, but frequencies of usages are different and high for only few sets of data. Bus encoding scheme suggested with the above fact is called as frequent value encoding (FVE) scheme. This paper provides mathematical model of FVE scheme. Paper aims at providing a framework for evaluation of bus encoding algorithms for 8 to 64-bit information flowing in computing system. Probabilistic model has been drawn and result shows efficiency of FVE scheme.
This work uses switch-level Verilog to simulate entire benchmarks using transistor level schematics and post-layout capacitance extraction. By translating a schematic netlist into a transistor level Verilog netlist, thousands of benchmark cycles can be simulated in minutes or hours compared with only tens of cycles using a fast spice simulator. This difference in simulation speed enables simulating an entire benchmark instead of trying to guess what a good spice simulation window is. This flow has been used extensively for power estimation and optimization of custom-based cache designs integrated into Qualcomm's 45 nm low power DSPs.
Due to the hot-electron effect and reliability, it is necessary to reduce the supply voltage of integrated circuit in CMOS sub-micro technologies. Low-voltage low-power circuit design is an important research in recent years. In this paper, the motivation and challenges of CMOS low-voltage low-power circuit are overall addressed. Furthermore, various circuit design techniques are described.
We give an overview of methods for modeling and system level design of mixed HW/SW/Analog systems. For abstract, functional
modeling we combine Kahn Process Networks and Timed Data Flow Graphs. In order to model concrete architectures, we combine
KPN and TDF with transaction level modeling. We describe properties and issues raised by the combination of these models and
show how these models can be used for executable specification and architecture exploration. For application in industrial
practice we show how these models and methods can be implemented by combining the standardized SystemC AMS and TLM extensions.
KeywordsAnalog/Digital Co-Design-KPN-Timed Data Flow-System Synthesis-Refinement-Refactoring-SystemC AMS extensions
Low-power design is an important research in recent years. A huge amount of papers in the open literature until now were proposed to deal with various low-power issues, including technology innovation, circuit/logic design techniques, algorithm realization, and architecture/system selection. Due to the high-energy electron effect and reliability consideration, it is necessary to further reduce the supply voltage of integrated circuit in CMOS sub-micro technologies. However, it is hard to get a whole view for various low-power low-voltage techniques in a short time. In this paper, the motivations and challenges of CMOS low-voltage low-power circuit are addressed. Various design methodologies are surveyed and summarized in whole. The paper attempts to quickly give readers a full-view conception in low-voltage low-power CMOS system design.
In this paper, we explore various design issues for coordinated distributed power management (CDPM) policies in wireless video sensor networks (VSNs). These CDPM policies help to efficiently power manage such networks while benefiting from the advantages gained by using distributed techniques. The design issues we explore include power management under dynamic and adaptive timeout thresholds, two-hop broadcast information dissemination, hybrid CDPM, and remote wakeup. Our investigations use an advanced, event-triggered VSN simulator, as well as a set of VSN prototype nodes we built as a proof-of-concept. Our prototype network includes four digital signal processing (DSP)-based wireless video nodes which form a small multi-hop network. Last but not least, we propose a novel analytical approach to predict the CDPM policy performance, and show that this analytical method matches the measured power savings in the prototype.
