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Example of chromosomes in the PLA. Two types of chromosomes are noticeable, the ch_and for the AND plane and the ch_or for the OR plane.
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Evolutionary algorithms are used for solving search and optimization problems. A new field in which they are also applied is evolvable hardware, which refers to a self-configurable electronic system. However, evolvable hardware is not widely recognized as a tool for solving real-world applications, because of the scalability problem, which limits t...
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... circuits, the most common are the: • Field Programmable Gate Array (FPGA) based structure used by: Tyrrell [11] and Thompson [12] to evolve robot controllers, and by Vinger [13] and Gwaltney [14] to design digital filters. • Field Programmable Transistor Array (FPTA) structure used by Stoica et al. to design fault tolerant very large scale integrated (VLSI) circuits [15]. PLA structure used by: Arslan et al. [17] to evolve digital filters and by Stomeo et al. [18] to design logic circuits. In this paper a new genetic algorithm, particularly designed for the evolution of logic circuits based on a PLA (Programmable Logic Array) structure is presented. A PLA was chosen for its structure, which is good for designing combinational logic circuits in VLSI and for its simplicity, regularity and flexibility. Another reason for having chosen a PLA instead of FPGA as structure for the evolution of digital logic circuits is because the permitted connectivity between logic gates within a PLA is smaller; therefore a reduction of the genotype length could be easily achieved. This helps the evolution of digital circuits. However the presented algorithm could be implemented into FPGA, initial work is given in [19]. The efficiency of the proposed algorithm has been examined using three test benches: the adders and the multipliers, both commonly used within the evolvable hardware community, and the MCNC benchmark traditionally used in logic design. This algorithm has proven itself to be very fast during the design process, as fewer generations are required to design the circuit. It has also demonstrated the ability to optimize the evolved circuits. Based on the results obtained for the evolved circuits, the proposed method also outperforms human design in terms of design cost. The simulation results of this new method have shown that it is able to design circuits faster than the fastest existing methods (know to the authors), which are Embedded Cartesian Genetic Programming (ECGP) [16] and Traceless Genetic Programming [20]. In the following sections the proposed genetic algorithm, together with the initialization, evaluation, selection and reproduction mechanisms are presented. This is followed by an explanation of the fitness value calculation, where a numeric example is also supplied. In Section III, the optimization within the proposed algorithm is outlined. In Section IV the experimental results obtained for the designed logic circuits together with an analysis of the initial data used for the simulations are presented. In Section V an analysis of the results found and the benefits of the proposed genetic algorithm are highlighted and compared with other similar techniques. Section VI concludes and summarizes the content of the paper. II. A N OVEL G ENETIC A LGORITHM In this section an introduction to the proposed method is firstly given, which outlines the motivation for the development of this new genetic algorithm. The initial section contains the description of the terms used to illustrate the proposed algorithm. The following sections explain the algorithm, together with chromosome representations, selection, reproduction mechanisms and fitness value calculations. The genetic algorithm described in this paper is intended for the design of combinational logic circuits based on a PLA structure. The key motivation for designing this algorithm is to have a fast configuration of the combinational logic circuits. The main characteristics of the proposed method are the use of several populations in parallel, and the construction of one population from the elitism’s pool (which contains the best chromosomes of each population). In order to describe the proposed algorithm, the evolution of a simple circuit is considered. Supposing that a circuit based on a PLA structure with 4 inputs should be evolved. Therefore the evolutionary algorithm should set the correct connections in the AND plane (for each interconnection the possible choices in the AND plane are “connect to 1”, “connect to 0” or “not connect”) and in the OR plane (the choices are “connected” or “not connected”). For the proposed algorithm (as reported in Figure 1) two different types of chromosomes have been ...
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... population contains all the chromosomes of the AND plane and all the chromosomes of the OR plane (see Figure 2) of the Programmable Logic Array. The proposed algorithm makes use of a multi-population of individuals. All the chromosomes of each population will be evaluated by the proposed algorithm and new populations of chromosomes will be created. The old populations will be replaced by those newly generated populations. The proposed genetic algorithm consists of the same mechanisms of the simple genetic algorithm [23][24] which are: initialization, evaluation, selection and generation. All these mechanisms are described in the next sections. Supposing that, for a particular experiment, N populations have been taken into account. At the initialization stage, all the chromosomes of the N populations have been randomly initialized. For the evaluation stage, each chromosome of each population will be individually evaluated. The evaluation is performed by analyzing and comparing the chromosome’s output with the truth table, which describes the digital circuit. The fitness value is calculated according to the quality of the evaluated chromosome. See Section II.F for more details on how the fitness value is calculated. During the evaluation stage a table, called the fitness’s value table , which contains the fitness’s value of each chromosome that is participating in the evolution of the digital circuit, is generated (see Figure 3). The table in Figure 3 refers to the fitness evaluation case of only the AND_PLANE. The fitness’s value table for the OR_PLANE is not given because it is similar. Each chromosome of each population is evaluated and its fitness’s value is stored in the fitness’s value table . In genetic algorithms, the selection mechanism is usually based on choosing the best individuals of a population. The generations of a new population is based on mating the chosen individuals using genetic operators. The most common genetic operators are the mutation, the crossover and the elitism. In evolvable hardware one single individual is generally not able to configure the entire circuit, especially for complex tasks. Usually, for the design of large circuits, several chromosomes should be linked together, since one chromosome represents a circuit configuration, which could be part of the entire design. In this novel genetic algorithm the selection of individuals is based on two stages. In the first stage the best populations (BPs) will be selected for the reproduction. The best populations are the populations with highest fitness’s value. The fitness value of one population is the average of all chromosomes’ fitness’s value. In order to accomplish this first selection a FVP (Fitness Value of the entire Population) vector is generated (see Figure 4) which contains the fitness value of each evaluated population. The second stage is performed in order to avoid chromosomes being allocated to solve the same regions of the solution space. This is possible because of the nature of the chromosome’s encoding used for the design of the PLA (see chromosome’s structure in Figure 1). By applying the proposed selections a new population is created as shown in Figure 4. This population is referred to here as: best built population, which is the population created by collecting the best chromosome from each region of the solution space. The reproduction of new populations is obtained by applying the mutation operator to the selected individuals. The new populations are generated in the following way (supposing that N is the total number of populations that are involved in the ...
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... the evolutionary algorithm should set the correct connections in the AND plane (for each interconnection the possible choices in the AND plane are "connect to 1", "connect to 0" or "not connect") and in the OR plane (the choices are "connected" or "not connected"). For the proposed algorithm (as reported in Figure 1 • ch_and, which represents a single column of possible connections inside the AND_PLANE. ...
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... second stage is performed in order to avoid chromosomes being allocated to solve the same regions of the solution space. This is possible because of the nature of the chromosome's encoding used for the design of the PLA (see chromosome's structure in Figure 1). By applying the proposed selections a new population is created as shown in Figure 4. ...
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Citations
... This work helps us to solve the promising approach towards autonomous and online reconfigurable machines capable of adapting and providing the best approach to real-world problems. Stomeo et al. have proposed a brand-new Genetic Algorithm for hardware evolution [4]. ...
... The configuration genome data generation is through EA, while the genome data format is Cartesian Genetic Programming (CGP) [5,6]. The CGP data generation is through HsClone algorithm, while other EA are also planned to be tested [7]. ...
In deep space systems, it is necessary to design reconfigurable system with fault tolerance. The delay in communication and the unpredictable failures can be detrimental to the space systems. The emerging field of embryonics, inspired from biological processes, provides in-built self-repair features. The embryonic circuit growth and its operation are decided by the stored genome configuration data. The embryonic cellular structure has in-built fault tolerance due to its structure. Each cell contains the total genome data of fabric, so that in case of any one cell failure, the data can be copied to spare cell. The fault detection technique at cell level has been explored in this chapter. The novel embryonic architecture with BIST that is proposed in this chapter is evolved from the concept of cloning used by biological cell to grow into a bigger system. The embryonic architecture is integrated with self-test and self-repair functions. In case the fault detection is possible at cell level, the faulty cell isolation is easy to implement. A novel embryonic fabric architecture with built-in self-test is presented. The design is coded using verilog and simulated for 1-bit adder and 2-bit comparator cell design. The genome data are generated through evolutionary algorithm and decoded as Cartesian Genetic Programming (CGP).
... The configuration genome data is generated using a GA, whereas the format of the genome data is Cartesian Genetic Programming (CGP) [12,13]. HsClone and OIMGA algorithms are used to generate CGP data, however, tests of other GA are also planned [14]. Embryonic cells, switch boxes, and the fabric controller module constitute the novel embryonic fabric that is being proposed. ...
The embryonic architecture, which draws inspiration from the biological process of ontogeny, has built-in capabilities for self-repair. The embryonic cells have a complete genome, allowing the data to be replicated to a cell that is not defective in the event of a cell failure in the embryonic fabric. A novel, specially designed genetic algorithm (GA) is used to evolve the configuration information for embryonic cells. Any failed embryonic cell must be notified by the proposed Built-in Self-test (BIST) module of the embryonic fabric.In this study, an effective centralized BIST design for a novel embryonic fabric is suggested. If the self-test mode is activated, the proposed BIST scans every embryonic cell. To optimize the data size, the genome or configuration data of each embryonic cell is decoded using the Cartesian Genetic Programming (CGP) format. This study evaluates the GA’s performance on 1-bit adder and 2-bit comparator circuits present in embryonic cells. Fault detection at every cell is made possible by the BIST module’s design. Additionally, the CGP format can offer gate-level fault detection. Customized GA and BIST are coupled with the novel embryonic architecture. The embryonic cell can perform self-repair through the process of scrubbing data for temporary defects.KeywordsBio-inspired systemsEmbryonicsEmbryonic fabricBISTSelf-testGenetic Algorithm
... The configuration genome data generation for embryonic cell is through GA, while the genome data format is Cartesian Genetic Programming (CGP) [11] [12]. The CGP data generation is through HsClone and OIMGA algorithms, while other GA are also planned to be tested [13]. ...
... Genetic algorithms (GA), a heuristic, are best known for their ability to find outstanding solutions for various applications [1]. As an example, Stomeo et al. proposed a genetic algorithm designed for evolvable hardware such as evolving logic circuits [2]. ...
Technology mapping is the transformation of a general Boolean logic network into a functional equivalent K-LUT network that can be implemented by the target FPGA device. Because an FPGA architecture is pre-determined, technology mapping is limited to the available resources. However, circuits can be optimized before the low-level synthesis phase. Odin II, part of the Verilog-to-routing project, is responsible for synthesis and elaboration. In the partial mapping phase of Odin II, some modifications are still possible for high-level modules—adder, multiplier—when there is no hard block available. When Odin II performs partial mapping to create soft logic, we can choose which implementation of a high-level module works best with respect to the desired goals: area versus speed. In this paper, we describe a method to modify circuit characteristics based on placement criteria. More specifically, after partial mapping circuit components during Verilog HDL code synthesis, there are still potential modifications in soft-logic circuit generation. We propose using a genetic algorithm during synthesis to adjust soft-logic circuit implementation in order to achieve the desired synthesis goal. We show that the approach provides promising results for a marginal cost in runtime.
... The parameters of the search algorithms are maintained same throughout all the experiments. Here, a tournament selection method of selecting the best configuration is preferred, with a single point crossover and random one-bit mutation (Stomeo et al., 2006). A group of five populations were selected for each tournament. ...
... The parameters of the search algorithms are maintained same throughout all the experiments. Here, a tournament selection method of selecting the best configuration is preferred, with a single point crossover and random one-bit mutation (Stomeo et al., 2006). A group of five populations were selected for each tournament. ...
... Gallagher, Vigraham, and Kramer proposed a family of compact genetic algorithms that could be integrated in digital systems without a substantial increase in size and complexity [153]. Stomeo, Kalganova, and Lambert presented a scalable GA built on a PLA for the design of digital circuits that could evolve faster than a traditional GA [154]. Another enhanced GA was proposed in [155] to reduce the evolution time and the required computations. ...
... FPGA-based EHW systems could find an unconventional solution using the underlying physics of the substrate, a solution that would not be considered by human intelligence itself. The significance of this work was (1) proving that an EHW can find solutions that circuit designers do not know about, (2) FPGAs are good hosts for EHW systems, and (3) with novel EAs [153,151,155,152,154]. There were no EHW implementations that were constructed with a novel reconfigurable hardware core and novel EA; our proposed system is the first that includes both. ...
Evolvable hardware (EHW) is a powerful autonomous system for adapting and finding solutions within a changing environment. EHW consists of two main components: a reconfigurable hardware core and an evolutionary algorithm. The majority of prior research focuses on improving either the reconfigurable hardware or the evolutionary algorithm in place, but not both. Thus, current implementations suffer from being application oriented and having slow reconfiguration times, low efficiencies, and less routing flexibility. In this work, a novel evolvable hardware platform is proposed that combines a novel reconfigurable hardware core and a novel evolutionary algorithm.
The proposed reconfigurable hardware core is a systolic array, which is called HexArray. HexArray was constructed using processing elements with a redesigned architecture, called HexCells, which provide routing flexibility and support for hybrid reconfiguration schemes. The improved evolutionary algorithm is a genome-aware genetic algorithm (GAGA) that accelerates evolution. Guided by a fitness function the GAGA utilizes context-aware genetic operators to evolve solutions. The operators are genome-aware constrained (GAC) selection, genome-aware mutation (GAM), and genome-aware crossover (GAX). The GAC selection operator improves parallelism and reduces the redundant evaluations. The GAM operator restricts the mutation to the part of the genome that affects the selected output. The GAX operator cascades, interleaves, or parallel-recombines genomes at the cell level to generate better genomes. These operators improve evolution while not limiting the algorithm from exploring all areas of a solution space.
The system was implemented on a SoC that includes a programmable logic (i.e., field-programmable gate array) to realize the HexArray and a processing system to execute the GAGA. A computationally intensive application that evolves adaptive filters for image processing was chosen as a case study and used to conduct a set of experiments to prove the developed system robustness. Through an iterative process using the genetic operators and a fitness function, the EHW system configures and adapts itself to evolve fitter solutions. In a relatively short time (e.g., seconds), HexArray is able to evolve autonomously to the desired filter.
By exploiting the routing flexibility in the HexArray architecture, the EHW has a simple yet effective mechanism to detect and tolerate faulty cells, which improves system reliability. Finally, a mechanism that accelerates the evolution process by hiding the reconfiguration time in an “evolve-while-reconfigure” process is presented. In this process, the GAGA utilizes the array routing flexibility to bypass cells that are being configured and evaluates several genomes in parallel.
... Divide-and-conquer and incremental evolution methods decompose a complex system into many simpler sub-systems, evolve these sub-systems and then assemble them. While some researchers focused on decreasing the computation complexity, they proposed the variable length chromosome [13] and dynamic mutation rate [14], and so on. In fact, if we decrease the computation complexity of the circuit evolution, and combine with the divide and conquer method, it will be effective to improve the scalability problem. ...
... The SLP (Short Link Priority) mutation Evolutionary Strategy (ES) we proposed in [15] was introduced in Generalized Disjunction Decomposition (GDD) to accelerate the evolutionary design. The Circuits we design are FPGA (Field Programmable gate Array)-based circuits and the design method are based on CGP (Cartesian Genetic Programming) [3, 14]. During the evolution of the cell array using CGP, SLP-Mutation ES is able to decrease the search space and accelerate the generation of full functional circuit, but it can't evolve more complex circuits. ...
... The GA is a method based on a natural evaluation and it aims to search for a global optimum solution from the entire search space. The GA has been successfully applied in many practical applications (Allen and Karjalainen, 1999; Kim et al., 2005; Stomeo et al., 2006; Ran et al., 2010) and has recently been introduced to the field of GPS data processing (Xu et al., 2002; Wu et al., 2007; Mosavi and Divband, 2010; Liu et al., 2010). In this paper, the GA is proposed as a suitable method to optimize the combination of GPS satellites in kinematic positioning. ...
The basis of high precision relative positioning is the use of carrier
phase measurements. Data differencing techniques are one of the keys to
achieving high precision positioning results as they can significantly
reduce a variety of errors or biases in the observations and models.
Since GPS observations are usually contaminated by many errors such as
the atmospheric biases, the receiver clock bias, the satellite clock
bias, and so on, it is impossible to model all systematic errors in the
functional model. Although the data differencing techniques are widely
used for constructing the functional model, some un-modeled systematic
biases still remain in the GPS observations following such differencing.
Another key to achieving high precision positioning results is to fix
the initial carrier phase ambiguities to their theoretical integer
values. To obtain a high percentage of successful ambiguity-fixed rates,
noisy GPS satellites have to be identified and removed from the data
processing step. This paper introduces a new method using genetic
algorithm (GA) to optimize the best combination of GPS satellites which
yields the highest number of successful ambiguity-fixed solutions in
kinematic positioning mode. The results indicate that the use of GA can
produce higher number of ambiguity-fixed solutions than the standard
data processing technique.
