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Fine pitch BGAs and chip scale packages have been developed as an
alternative to direct flip chip attachment for high-density electronics.
The larger solder sphere diameter and higher standoff of CSPs and fine
pitch BGAs improve thermal cycle reliability while the larger pitch
relaxes wiring congestion on the printed wiring board. Fine pitch BGAs
a...
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Citations
... high acceleration performance, thermal cycle performance, and fatigue life [16]. However, simply applying an underfill layer also brings side effects from the thermal-mechanical perspective. ...
In this paper, an experimental approach is presented to investigate the influence of second level underfill on the thermomechanical behavior of two BGA packages during thermal cycles. Two different flip chip packages with two major underfill reinforcement methods (corner bonding and full bottom surface bonding) and no-underfill were studied. To quantitatively measure the deformation of solder balls, all the BGA packages were cross-sectioned before thermal cycles. The two-dimensional digital image correlation (DIC) technique was used to capture the in-plane deformation of the critical solder ball in thermal cycling intervals. The accumulated plastic strain of the BGA solder was calculated after every 10 thermal cycles. The temperature of each cycle was set from −40 to 100 °C at a 20°C/second rate. The experiment results showed that Package A with fully underfilled and corner underfilled both alleviated the averaged plastic strain on the critical solder ball in comparison with the no-underfilled Package A. However, Package B with corners underfilled had a larger plastic strain than the package without underfill. The material properties of underfill applied in the two reinforcement methods are identical. The results indicate that inappropriate underfilling methods can adversely affect the thermomechanical reliability of the packages. The underfill material and reinforcement methods are associated with the stiffness rigidity and the compact CTE of the package itself. In the respect of thermomechanical reliability, second level underfilling should be individually specified for varied packages.
... An underfill layer helps protect and prolong the life of flip-chip interconnects. The demand for greater I/O density in advanced electronics packages has shrunk the solder joint size significantly, and the fine pitch BGA is potentially the future of 2 nd level interconnection [1][2][3]. Fine-pitch BGA packages have raised great concerns on general package reliability as solder joint reliability deteriorates significantly against mechanical drop incidents, shock events or thermal cycling as consequences of the reduction of solders joint size and pitch. Hence, applying an underfill layer at the board level to protect BGA solders from mechanical sources has been known as a potential solution, especially for handheld devices which have at high potential experiencing drop or shock events. ...
... Some aspects of the process may appear redundant or inefficient at first sight. In its most popular implementation, a soldering flux is first applied, only to be painstakingly washed away after chip bonding, to avoid underfill reliability issues [1][2][3][4]. The flux is of course needed to prevent oxidation during the high temperature reflow, which converts part of the chip metallurgy to intermetallics, which can be less resilient than solder [5][6][7]. ...
Since its inception, the flip-chip bonding process has allowed for an ever-increasing density of interconnections in microelectronic packages. While traditional mass reflow (MR) soldering continues to be useful, alternative techniques such as thermal compression bonding (TCB) have evolved to support denser interconnection technologies. However, the TCB process requires relatively long cycle times and is sensitive to chip site warpage, as well as solder volume, bonding force or alignment variations. We report on this study a new solid-state thermocompression bonding process. It relies on temporary mechanical joints that are formed at the beginning of the packaging process, using pressure at a temperature below the solder melting point. The electrical interconnections are formed when the solder joints are completely remelted at the end of the packaging process, when the BGA solder balls are soldered to the substrate. We call this the Bond At The End (BATE) process. We have investigated the critical bonding parameters needed to achieve the initial temporary bond. The optimal bonding parameters were found to be 200°C in temperature, 0.25 N/bump in force, with a 4.5 s dwell time and 6 s total bonding duration. Applying an Ar/H2 plasma treatment before the assembly process also improved the bonding strength. A thorough investigation of the mechanical anchoring mechanism was carried out. Strong mechanical joining appears to be the result of the migration of interfacial grains boundaries and of the resulting interlocking of the solder bump surfaces. The quality of the final joints after BGA reflow was characterized with optical micrographs, x-ray imaging, and C-mode scanning acoustic microscopy. Under the optimal bonding conditions, we observed a high electrical yield and good reliability in thermal cycling, consistent with finite element modeling indicating a normal thermal stress in the final solder joints.
... Although several possible FC encapsulants and several ways of applying them were initially considered (about three decades ago) [1], it was the underfill encapsulation that became the today's technology of choice [2][3][4][5][6][7][8]. Because the main reason for introducing FC and FPBGA technologies was insufficient reliability of FC and FPBGA technologies, the overwhelming majority of publications were and still are dedicated to the reliability issues and challenges (see, e.g., [9,10]), as well as to the selection of the appropriate FC or FPBGA technology and encapsulant [11][12][13][14][15].Ceramic packages are, as is known, more reliable than plastic packages, both because a better thermal match of ceramic materials with Si and because of high reliability of these materials The early investigations of FC technologies were geared therefore to ceramic packages (see, e.g., [16]). ...
In this review, some major aspects of the current underfill technologies for flip-chip (FC) and fine-pitch-ball-grid-array (FPBGA), including chip-size packaging (CSP), are addressed, with an emphasis on applications, such as aerospace electronics, for which high reliability level is imperative. The following aspects of the FC and FPGGA technologies are considered: attributes of the FC and FPBGA structures and technologies; underfill-induced stresses; the roles of the glass transition temperature (Tg) of the underfill materials; some major attributes of the lead-free solder systems with underfill; reliability-related issues; thermal fatigue of the underfilled solder joints; warpage-related issues; attributes of accelerated life testing of solder joint interconnections with underfills; and predictive modeling, both finite-element-analysis (FEA)-based and analytical ("mathematical"). It is concluded particularly that the application of the quantitative assessments of the effect of the fabrication techniques on the reliability of solder materials, when high reliability is imperative, is critical and that all the three types of research tools that an aerospace reliability engineer has at his/her disposal, should be pursued, when appropriate and possible: experimental/testing, finite-element-analysis(FEA) simulations, and the "old-fashioned" analytical ("mathematical") modeling. These two modeling techniques are based on different assumptions, and if the computed data obtained using these techniques result in the close output information, then there is a good reason to believe that this information is both accurate and trustworthy. This effort is particularly important for high-reliability FC and FPBGA applications, such as aerospace electronics, as the aerospace IC packages become more complex, and the requirements for their failure-free operations become more stringent.
... Peng et al. [23] found that the drop performance of an unfilled commercial underfill was better than that of a filled underfill; however, they did not report the adhesive modulus or consider the effects of a varying fillet size. ...
... Some of the options to improve BLI mechanical reliability include localized stiffening of the board through backing plates and stiffeners [4,5], addition of board supports to reduce board flexure and adoption of adhesive bonds to reduce the BLI stresses between the component substrate and board surface [6]. The adhesive bonds used can either be a full capillary flow underfill [7][8][9] or bonding of component to board in the edges and corners [10][11][12][13][14]. However the former solution, full capillary flow underfill, increases both the cost of production and assembly cycle times in manufacturing and this must be considered against the reliability improvements. To reduce the costs of full capillary flow underfill application, edge bonding and corner processes have been developed. ...
This paper presents the four-point bend test results for edge and corner bonded 0.5mm pitch lead-free package stackable very thin fine pitch ball grid arrays (PSvfBGAs) as package-on-package (PoP) bottom packages on a standard IPC/JEDEC bend test board. The tests were carried out based on the above standard with a 30mm loading span, 90mm support span and 7.5mm/s crosshead speed. The daisy chain resistance, strain, crosshead displacement and load of each PSvfBGA were measured and a 20% increase in the resistance was used as the failure criterion. Materials used in this study were a UV-cured acrylic edge bond adhesive, a thermal-cured epoxy edge bond adhesive and a thermal-cured epoxy corner bond adhesive. The test results show that all of them can improve the bend performance significantly; especially the edge bond high module epoxy increased the crosshead displacement, strain and bending force when mechanical damage occurred by 33.46%, 26.74% and 3.05% respectively. Failure analysis indicated that the predominant failure site was PCB pad lift/cratering regardless of with or without adhesives. The 3D quarter finite element model was also built to further study the improvement mechanism of bend performance by these adhesives.
... However, the IC and PCB assembly manufacturers desired a board level test method that is independent of the portable product. Peng et al. [19] of Auburn University and Mishiro et al. [20] of Fujitsu performed drop-impact tests on bare PCB assemblies. For the former, the orientation of the bare PCB was ''guided" by a tube to enable vertical impact of the PCB assembly. ...
The reliability of electronics under drop-shock conditions has attracted significant interest in recent years due to the widespread use of mobile electronic products. This review focuses on the drop-impact reliability of lead-free solder joints that interconnect the integrated circuit (IC) component to the printed circuit board (PCB). Major topics covered are the physics of failure in drop-impact; the use of board level and component level test methods to evaluate drop performance; micro-damage mechanisms; failure models for life prediction under drop-impact; modelling and simulation techniques; and dynamic stress–strain properties of solder joint materials. Differential bending between the PCB and the IC component is the dominant failure driver for solder joints in portable electronics subjected to drop-impact. Board level drop-shock tests correlate well with board level high speed cyclic bending tests but not with component level ball impact shear tests. Fatigue is the micro-damage mechanism responsible for the failure of solder joints in the drop-shock of PCB assemblies and the fatigue strength of solder joints depends strongly on the strain rate, test temperature, and the sequence of loading. Finally, tin-rich lead-free solders exhibit significantly higher strain rate sensitivity than eutectic SnPb solder.
... This approach places pressure on the time-to-market constraint. The second approach is to use underfills to mechanically reinforce the CSP solder joints [1][2][3][4][5][6]. This adds cost and cycle time to the manufacturing process. ...
Three underfill options compatible with lead-free assembly have been evaluated: capillary underfill, fluxing underfill, and corner bond underfill. Chip scale packages (CSPs) with eutectic Sn/Pb solder were used for control samples. Without underfill, lead-free and Sn/Pb eutectic drop test results were comparable. Capillary flow underfills, dispensed and cured after reflow, are commonly used in CSP assembly with eutectic Sn/Pb solder. With capillary flow underfill, the drop test results were significantly better with lead-free solder assembly than with Sn/Pb eutectic. Fluxing underfill is dispensed at the CSP site prior to CSP placement. No solder paste is printed at the site. The CSP is placed and reflowed in a standard reflow cycle. A new fluxing underfill developed for compatibility with the higher lead-free solder reflow profiles was investigated. The fluxing underfill with lead-free solder yielded the best drop test results. Corner bond underfill is dispensed as four dots corresponding to the four corners of the CSP after solder paste print, but before CSP placement. The corner bond material cures during the reflow cycle. It is a simpler process compared to capillary or fluxing underfill. The drop test results with corner bond were intermediate between no underfill and capillary underfill and similar for both lead-free and Sn/Pb eutectic solder assembly. The effect of aging on the drop test results with lead-free solder and either no underfill or corner bond underfill was studied. Tin/lead solder with no underfill was used for control. This test was to simulate drop performance after the product has been placed in service for some period of time. There was degradation in the drop test results in all cases after 100 and 250 h of storage at 125°C prior to the drop test. The worst degradation occurred with the lead-free solder with no underfill.
... The main reliability challenge in the past has been mechanical failures such as separation of assemblies, dislodging of batteries, disengaging of snap fits, cracking of the housing or liquid crystal display, and wear-and-tear of components [1][2][3][4][5]. More recently, there have been increased concerns about electrical failure, particularly in the interconnections between the IC packages and the printed circuit board (PCB), known as board level interconnections [6][7][8][9][10][11][12][13][14][15][16][17]. This problem was serious enough to justify the inclusion of a new JEDEC board level test standard [18]. ...
... Different techniques for performing board level drop impact test have been reported. These include free-drop of a bare board assembly onto a hard surface [9,14,17], dropping the PCB mounted into a test phone onto a hard surface [7], striking of the board assembly with a steel ball [13], guided-drop of the board assembly from a drop test fixture onto a surface [12,13]. A variation of the guided-drop test has a hemisphere attached at the center bottom of the metal base [11,16], presumably to ensure consistent point impacts. ...
This paper provides a comprehensive summary of research activities focusing on the reliability of board level interconnections in drop impact, covering experimental work together with analytical and numerical modeling studies. These activities involve investigating (i) the dynamics of the PCB in product level and board level drop impact; (ii) the failure drivers: inertia force, differential flexing, and knocking; (iii) the relations among the PCB flexural modes, PCB strain, and interconnection stress/strain; (iv) high-strain-rate material characteristics; and (v) failure models
... Studies have shown that filler settling can deteriorate the potential reliability performance of the underfill material [7], [13]. In these studies, a modified epoxy resin with and without silica filler pre-filled was used as underfill materials, and thermal shock reliability tests were conducted. ...
Underfills can dramatically improve flip chip reliability. However, the fillers used in some underfills can be dispersed unevenly, causing less than optimal reliability. In this study, underfill dispensing was conducted using various fill patterns. Experimental results show that particle settling occurs during the curing process, rather than during dispensing, and is affected by the difference between filler and matrix densities and underfill viscosity. Particle migration is a secondary mechanism, which causes uneven filler distribution. A vertically oriented transfer molding machine could help to mitigate settling.
