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This paper presents a successive approximation register (SAR) analog-to-digital converter (ADC) designed for a wireless power transfer system. This is a four–channel SAR ADC structure with 10-bit resolution for each channel, which can also be applied as a single 12-bit ADC. To reduce the area and the number of the required devices in the ADC module...
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Context 1
... is notable that, if the MSB-2 bit is determined to be zero, then the bottom plate of one of the capacitors in Figure 8 that is connected to V REF is switched back to zero, and then bit decision is continued in the RDAC. Figure 9 shows an example of bit decision in the RDAC. For this case, we assume that the three MSBs are 110. ...
Context 2
... this simulation, the number of samples is 100, the mean value is 1.799128 and the standard deviation is 666 µV, which is less than one LSB for the 12-bit operating mode. Figure 19 presents the power break-down of the design for 10-bit operating mode. As can be seen, RDAC, reference generator, and pre-amplifier power consumptions are dominant. ...
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Citations
... Effective number of bits (ENOB), power consumption, and conversion speed along with other parameters measure the performance of ADCs. With complementary metal-oxide-semiconductor (CMOS) technologies entering the submicron domain, the transistor sizing has been downscaled to a few nanometers [5][6][7][8][9]. For low power and medium conversion speed, the SAR type ADC is among the best available choices as in its operation, full conversion is divided into several comparison phases by using only one comparator [10]. ...
This paper presents a wide-range and low phase noise mm-Wave Voltage Controlled Oscillator (VCO) based on the transconductance linearization technique. The proposed technique eliminates the deep triode region of the active part of the VCO, and lowers the noise introduced by the gm-cell. The switch sizes inside the switched capacitor bank of the VCO are optimized to minimize the resistance of the switches while keeping the wide tuning range. A new layout technique shortens the routing of the VCO outputs, and lowers the parasitic inductance and resistance of the VCO routing. The presented method prevents the reduction of the quality factor of the tank due to the long routing. The proposed VCO achieves a discrete frequency tuning range, of 14 GHz to 18 GHz, through a linear coarse and middle switched capacitor array, and offers superior phase noise performance compared to recent state-of-the-art VCO architectures. The design is implemented in a 45 nm CMOS process and occupies a layout area (including output buffers) of 0.14 mm2. The power consumption of the VCO core is 24 mW from the power supply of 0.8 V. The post-layout simulation result shows the VCO achieves the phase noise performances of −87.2 dBc/Hz and −113 dBc/Hz, at 100 kHz and 1 MHz offset frequencies from the carrier frequency of 14 GHz, respectively. In an 18 GHz carrier frequency, the results are −87.4 dBc/Hz and −110 dBc/Hz, accordingly.
... Effective number of bits (ENOB), power consumption, and conversion speed along with other parameters measure the performance of ADCs. With complementary metal-oxide-semiconductor (CMOS) technologies entering the submicron domain, the transistor sizing has been downscaled to a few nanometers [5][6][7][8][9]. For low power and medium conversion speed, the SAR type ADC is among the best available choices as in its operation, full conversion is divided into several comparison phases by using only one comparator [10]. ...
This paper presents an energy-efficient low power 10-b 8-MS/s asynchronous successive approximation register (SAR) analog-to-digital (ADC) converter. An inverted common-mode charge recovery technique is proposed to reduce the switching energy and to improve the linearity of the digital-to-analog converter (DAC). The proposed switching technique consumes only 149 CVREF2 switching energy for the 10-bit case. A rail-to-rail dynamic latch comparator is implemented with adaptive power control for better power efficiency. Additionally, to optimize the power consumption and performance of the logic part, a modified asynchronous type SAR control logic with digitally controllable delay cells is adopted. An on-chip reference voltage generator is also designed with an ADC core for practical use. The structure is realized using 55-nm complementary metal–oxide–semiconductor (CMOS) process technology. The proposed architecture achieves an effective number of bits (ENOB) of 9.56 bits and a signal-to-noise and distortion ratio (SNDR) level of 59.3 dB with a sampling rate of 8 MS/s at measurement level. The whole architecture consumes only 572 µW power when a power supply of 1 V is applied.
... However, the linearity may be severely damaged because the fractional-value bridge capacitor is difficult to match and highly sensitive to the parasitic effect. This paper adopts a capacitor-resistor hybrid DAC structure (C-RDAC) [16][17][18][19][20]. By using this structure, the bridge capacitor can be eliminated while keeping a small input capacitance. ...
In this paper, an 8-channel 16 bit 200 kS/s successive approximation register analog-to-digital converter (SAR ADC) realized in 130 nm SOI CMOS technology is presented. A capacitor-resistor hybrid digital-to-analog converter (DAC) is adopted in this design to avoid the bulky capacitor array. In addition, an on-chip self-calibration technique is proposed to calibrate the mismatch of the capacitors in the DAC. To simplify the calibration logic of the resistor DAC, an auxiliary capacitor is added in the capacitor DAC to replace the resistor DAC for calibration. Moreover, the added auxiliary capacitor can also be utilized to correct the errors caused by the incomplete settling of reference voltage during the conversion. The measured results show that signal-to-noise-and-distortion-ration (SNDR) and spurious-free-dynamic-range (SFDR) compared with it without calibration are improved from 76.51 dB to 85.82 dB and 80.84 dB to 95.14 dB, respectively. The proposed ADC occupies an active area of 0.966 mm² and consumes a total power of 3.1 mW.
... Although the work in [21] shows a higher resolution, it has a larger area. The work in [20] has a lower area but at the same time lower ENOB. Table 2 compares the decimation filter with other works. ...
... Finally, Table 1 summarizes the performance of the SD-ADC, including SDM and decimation filter, and compares it with other ADC structures. The work in [20] has a lower area but at the same time lower ENOB. Although the work in [21] shows a higher resolution, it has a larger area. ...
This paper presents a second-order discrete-time Sigma-Delta (SD) Analog-to-Digital Converter (ADC) with over 80 dB Signal to Noise Ratio (SNR), which is applied in a signal conditioning IC for automotive piezo-resistive pressure sensors. To reduce the flicker noise of the structure, choppers are used in every stage of the high gain amplifiers. Besides, to reduce the required area and power, only the CIC filter structure is adopted as a decimation filter. This filter has a configurable structure that can be applied to different data rates and input signal bandwidths. The proposed ADC was fabricated and measured in a 0.18-µm CMOS process. Due to the application of only a CIC filter, the total active area of the SD-ADC and reference generator is 0.49 mm2 where the area of the decimation filter is only 0.075 mm2. For the input signal bandwidth of 1.22 kHz, it achieved over 80 dB SNR in a 2.5 MHz sampling frequency while consuming 646 µW power.
