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This paper represents a cycle-based logic simulation method using an LUT cascade emulator, where an LUT cascade consists of multiple-output LUTs (cells) connected in series. The LUT cascade emulator is an architecture that emulates LUT cascades. It has a control part, a memory for logic, and registers. It connects the memory to registers through a...
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DLSim is a digital logic simulator developed by our men-tor Richard M. Salter. What distinguishes DLSim from other digital logic simulators is its robust plug-in system. Working with the DLSim plug-in system this summer presented us with an opportunity to explore progressively more complicated digital logic circuits in a virtual envi-ronment. We se...
This paper presents a hybrid logic simulator using both an event-driven and a cycle-based methods. For special primitives such as memories and tri-state buffers, it uses an event-driven method. For other parts, it uses a cycle- based method using LUT cascade emulators. To simulate a large scale circuit, it partitions the circuit into smaller ones,...
Students of Computer Organization should be able to"learn by doing" at all levels of computer design. Digital logic cir- cuitry is frequently taught using simulation software, how- ever such platforms are often limited to exposing only a nar- row range of design levels. This paper describes how, in the new multilevel simulation system DLSim 3, we a...
Citations
... In this paper, to implement the multiple-output functions, functions are decomposed into single-output ones. However, decomposition into groups of a few functions also produces very good circuits [12]. Yet another possible extension is to use such partitions of the outputs. ...
First, this paper considers the number of LUTs to imple- ment logic functions based on MUX-based realization and cascade realization. This is useful to quickly estimate the number of LUTs to implement the functions on a FPGA. Second, this paper shows an algorithm to realize logic func- tions by 6-LUTs using cascade and MUX-based realiza- tions. It often produces smaller circuits than previous meth- ods when the number of the input variables is smaller than 16.
... Thus, a high-speed logic simulators is needed. We have proposed a new type of cycle-based logic simulator [10,8,9]. In this simulator, first, the given circuit is converted into LUT cascade, then the cell data is stored into the memory on the PC. ...
... However, when a component function is excessively complex, this method fails. In [9], we presented a method to partition the netlist. Although this method requires an extra time for evaluating connections between partitioned networks, it is applicable to a large scale circuit. ...
... Thus, we partition the netlist into small modules, and realize each module by an LUT cascade emulator. The greedy algorithm described in [9] partitions the netlist to reduce the number of interconnections. ...
This paper presents a hybrid logic simulator using both an event-driven and a cycle-based methods. For special primitives such as memories and tri-state buffers, it uses an event-driven method. For other parts, it uses a cycle- based method using LUT cascade emulators. To simulate a large scale circuit, it partitions the circuit into smaller ones, and realizes each part by an LUT cascade emulator. Next, it combines these emulators by interconnections. Since a mul- tiplier often requires large memories in an LUT cascade, an instruction of the processor is used instead of the LUT cas- cade. This will reduce the code size and the simulation time. Our experiment shows that proposed method is effective for circuits including arithmetic operations.
A decomposed multi-terminal multi-valued decision diagrams for characteristic function(MTMDDs for CF) represents decomposed circuits. It can represent complex functions compactly. This paper shows a machine that evaluates decision diagrams. First, we introduce the decomposed MTMDDs for CF. Then, we consider two instructions to evaluate the decomposed MTMDDs for CF. Next, we show a machine that evaluates the decision diagrams. We compare that machine with embedded processors. As for the power-delay product, our machine running at 100 MHz is 60.84 times smaller than Nios II processor running at 100 MHz, and it is 18.66 times smaller than Atom N455 processor running at 1.67 GHz.
Binary decision diagrams representing complex logic circuits require a large number of nodes. This paper shows a new method to represent logic circuits using multiple decision diagrams. First, a given logic circuit is converted into a direct acyclic graph~(DAG). Then, the DAG is decomposed into clusters. Next, clusters are represented by multi-terminal binary decision diagrams for characteristic function~(decomposed MTBDDs for CF). It represents a logic circuit more compactly than the conventional MTBDD for CF. Finally, the decomposed MTBDDs for CF are converted into the multi-terminal multi-valued decision diagrams for CF~(decomposed MTMDDs for CF) to be stored in the given memory size. Also, the decomposed MTMDDs for CF is faster to evaluate than the conventional MTMDD for CF using the same memory size on a BDD machine.
This paper first reviews the trends of VLSI design, focusing on the power dissipation and programmability. Then, we show the advantage of Quarternary Decision Diagrams (QDDs) in representing and evaluating logic functions. That is, we show how QDDs are used to implement QDD machines, which yield high-speed implementations. We compare QDD machines with binary decision diagram (BDD) machines, and show a speed improvement of 1.28-2.02 times when QDDs are chosen. We consider 1-and 2-address BDD machines, and 3- and 4-address QDD machines, and we show a method to minimize the number of instructions.
