Energy-band diagrams of CTF memory cell structures with Al  

Contexts in source publication

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... cell memory characteristics are observed by the capacitance-voltage (C-V ) measurement 14 To explain the above program/erase characteristics, we can utilize the energy-band diagrams of CTF memory cell structures with different gate materials. The energy-band diagram of CTF memory cell with a positive gate voltage applied is shown in Figure 4(a). When a positive volt- age is applied to the gate, electrons in Si conduction band tend to be injected to silicon nitride through the tunnel oxide, and most of them will be trapped in the silicon nitride and distribute within the silicon nitride. ...

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... n + poly-Si gate CTF memory cell has a larger electrostatic potential difference across the ONO layer in comparison with Al gate CTF memory cells. Accordingly, the electric field in the blocking oxide of n + poly-Si gate CTF memory cells becomes larger and the barrier width becomes narrower, as shown in Figure 4(a). Thus, n + poly-Si gate CTF memory cells have larger threshold voltage shifts after programming, as shown in Figure 3. ...

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... n + poly-Si gate CTF memory cells have larger threshold voltage shifts after programming, as shown in Figure 3. The energy-band diagram of CTF memory cell struc- ture with a negative gate voltage applied is shown in Figure 4(b). When a negative voltage is applied to the gate, holes in Si valence band tend to be injected into silicon nitride through tunnel oxide, and most of them will be combined with electrons that are trapped in silicon nitride, as depicted in Figure 4(b). ...

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... energy-band diagram of CTF memory cell struc- ture with a negative gate voltage applied is shown in Figure 4(b). When a negative voltage is applied to the gate, holes in Si valence band tend to be injected into silicon nitride through tunnel oxide, and most of them will be combined with electrons that are trapped in silicon nitride, as depicted in Figure 4(b). That is, a negative gate volt- age erases CTF memory cells mainly by hole injection. ...

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... as the erase voltage increases, the probability of the electron-back-tunneling from the gate to the silicon nitride increases. As shown in Figure 4(b), the electron- back-tunneling phenomenon counteracts erase operation, resulting in the non-fully erased state. In the case of the back-tunneling, the gate/blocking oxide energy barrier of the n + poly-Si gate is lower than that of Al gate, so that the back-tunneling current is higher. ...