Energy band diagram for the three possible operation regimes of the MOSFET. 

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Context 1

... H ( E ) is the Heaviside function ͓ H ( E ) 1 if E 0; H ( E ) ϭ 0 otherwise ͔ . As we will see in the next section, E FS Ϫ E v n ( x max ) depends on V GS and V DS . Equation ͑ 5 ͒ reveals three possible operation regimes depending on the lo- cation of the subbands with respect to the Fermi levels ͑ Fig. 3 ͒ . To discuss these regimes, we define E n ( x max ) as the or- dered set of energies E v n ( x max ), being E 1 ( x max ) the lowest energy in this set. a E FS E 1 ( x max ): At zero Kelvin the current is zero because the population of ϩ k x ( Ϫ k x ) states at source and drain contacts have not enough energy to transmit across the barrier towards the drain ͑ source ͒ . If the temperature is greater than zero, the tails of the Fermi functions extend above the barrier. Moreover, if the device is out of the equilibrium ( V DS Ͼ 0) some leakage current flows because the tail of f S ( E ) above the maximum of the barrier, which is transmitted towards the drain, is larger than the corresponding tail of f D ( E ) that cross the channel ballistically towards the source. This leakage current corresponds to the diffusion current. This regime takes place when V GS Ͻ V th , where V th ͑ threshold voltage ͒ is the gate voltage for the first subband to cross the Fermi level at the source; i.e., the gate voltage for which E 1 ( x max ) ϭ E FS . The situation described corresponds to the subthreshold regime. ͑ b ͒ E FS Ͼ E i ( x max ), where i у 1; and E FD Ͼ E j ( x max ), where j у 1: The forward I ϩ ͑ backward I Ϫ ) current is given by the electrons with energies between E i ( x max ) ͓ E j ( x max ) ͔ and E FS ( E FD ) ͑ at zero Kelvin ͒ . The net current is the difference I ϩ Ϫ I Ϫ , and the slope ͑ G ͒ of the output characteristic is an even multiple of the quantum conductance ( G 0 ): G ϭ dI / dV DS ϭ 2 M G 0 , where G 0 ϭ q 2 / ␲ ប ; the factor 2 arises from the two-fold degeneracy of each set of valleys and M is the number of subbands below E FD . This situation takes place when V GS Ͼ V th and V DS is low enough. It corresponds to the linear regime of the MOSFET operation. ͑ c ͒ E FS Ͼ E i ( x max ), where i у 1; and E FD р E 1 ( x max ): In this case, the forward current I ϩ is given by the electrons with energies between E i ( x max ) and E FS . The backward current I Ϫ is suppresed because the occupied Ϫ k x states at the drain contact cannot transmit across the barrier towards the source. This case corresponds to the saturation regime V GS Ͼ V th and V DS high ͒ , for which the current is independent of the applied source-drain voltage. The onset of the saturation regime occurs at the drain voltage V DS ,sat that makes E ( x ) ϭ E . In the last section we have derived the current equation of the quantum wire MOSFET in terms of the separation between the Fermi level and the bottom of the subbands at the maximum energy point ( x max ). The goal of this section is to find how this separation depends on the applied gate and drain voltages for the DG structure. We will assume that the two-dimensional short-channel effects are small ͑ future extensions of the compact model will deal with two- dimensional electrostatics ͒ . The potential and charge distribution of the intrinsic DG structure has been reported by Taur. 13,14 The electrostatic analysis was only done in the vertical direction, but it serves our purposes if we apply the results at the maximum energy point ( x max ). At this special point, the potential and charge distributions are essentially controlled by the electric field perpendicular to the silicon-insulator interface; the lateral electric field is close to zero, and the gradual channel ap- proximation applies. 15 The potential along the vertical direction (0 р z р t /2) is given by 13,14 ln cos e 0 z , 6 2 kT 2 ␧ Si kT where ␺ 0 ε ␺ ( z ϭ 0) is the potential at the center of the silicon film, ␧ Si is the permittivity of silicon and n i is the intrinsic carrier density ͑ see Appendix A for a detailed derivation of this quantity in a quantum wire ͒ . The surface potential is ␺ s ε ␺ ( z ϭ t Si /2); ␺ s is also related to V GS and t ox through the boundary condition at the silicon-oxide interface ...

Context 2

... E n is the separation of the bottom of the n th- subband from the bottom of the conduction band, for a two- dimensional infinite square-well potential ͑ see Appendix B ͒ ; E 1 ( x max ) is the energy of the lowest subband, and ⌬ E 1 is the separation between E 1 ( x max ) and the bottom of the conduction band. Equation ͑ 14 ͒ can be numerically solved for the only unknown E FS Ϫ E 1 ( x max ) for a given V GS and V DS . We present now an illustrative example using this model. In this section, we show calculations of the transconductance ͑ Fig. 4 ͒ and conductance ͑ Fig. 5 ͒ of a quantum wire DG-MOSFET at different temperatures. The silicon film thickness and width are 2 and 3 nm, respectively. The oxide thickness is 1.5 nm, and the gate electrodes have a midgap gate work-function ͑ 4.61 eV ͒ . In Figs. 4 ͑ a ͒ and 4 ͑ c ͒ we show the bottom of the subbands at the virtual cathode, the surface, and center potentials, and the normalized current ( qI / G 0 ), all of them plotted versus V GS ͑ the Fermi level E FS is taken as a reference ͒ . Figures 4 ͑ b ͒ and 4 ͑ c ͒ show the transconductance at low ͑ 40 K ͒ and high temperatures ͑ 300 K ͒ , respectively. The increase of the gate voltage induces more mobile charge at the virtual cathode, pulling down the maximum of the barrier ͑ respect to the Fermi levels ͒ in order to inject this incremental charge. For the low temperature case, when the gate voltage is below 0.8 V all the subbands are above E FS , and the device operates in the subthreshold region. In this regime, both the current and the transconduc- tance are close to zero. At 0.8 V the threshold voltage , the first subband ( E 1 1 ) intersects the Fermi level, producing the first peak of the transconductance, and the device enters the above threshold saturation region. The threshold voltage is Ϸ 0.7 V at 300 K because the tail of the Fermi function popu- lates subbands above the Fermi level, contributing to the current before the first crossing. By increasing the gate voltage the subbands cross the source and drain Fermi levels producing a structure of peaks and valleys on the transconductance. This is very clear at low temperature, but at room temperature the structure is partially lost because the large extension over the energies of the tail of the Fermi function. In Figs. 5 ͑ a ͒ and 5 ͑ c ͒ we show the bottom of the subbands at the virtual cathode and the normalized current, plotted versus V DS . Note first of all the slight decrease of the bottom of the subbands with V DS . The mobile charge at the virtual cathode is constant, because V GS is fixed. When V DS is raised, the population of Ϫ k x states at the virtual cathode is gradually reduced. To maintain Q constant, the maximum of the barrier must be pulled down in order to inject more ϩ k x states from the source, and balance the Ϫ k x states. This effect occurs until the negative states population is totally suppressed at V DS,sat ϭ 0.55 V. For low V DS , four subbands are below the two Fermi levels, and the conductance is about 8 G 0 ͑ it would be exactly 8 G 0 at zero Kelvin ͒ , each subband contributing with 2 G 0 . Increasing V DS , the fourth, third, second, and first subband cross successively E FD , reducing the conductance to about 2 G 0 each one ͓ Fig. 5 ͑ b ͔͒ . The first subband crossing with E FD determines the onset of the saturation region. At T ϭ 300 K, saturation occurs at V DS,sat ϭ 0.6 V. The conductance structure is partially lost at this temperature because the tail of the Fermi function smooth the conductance ͓ Fig. 5 ͑ d ͔͒ . If the DG-MOSFET has a very large width W , the confinement in the y -direction is lost, and the electron gas movement is restricted only in the z -direction. In this limit case, the compact model provides good results for the voltage- current characteristics. A width W ϭ 500 nm is large enough to remove the confinement in the y -direction. We want to check if the important parameters like the threshold voltage, subthreshold swing, off-current, and on-current are well predicted by our model. For this purpose we have performed a simulation using a DG-MOSFET, with a channel length of 40 nm, a silicon film thickness of 1.5 and 3 nm, an oxide thickness of 1.5 nm, and gate electrodes having a work function of 4.25 eV. The device was simulated at low ͑ 100 K ͒ and room temperature ͑ 300 K ͒ . The results of our model are compared with accurate self-consistent simulations provided by the nanoMOS simulator, 8,9 based on the nonequilibrium Green’s functions. 17,18 This simulator deals with quantum well DG-MOSFETs, and it can consider up to six two- dimensional subbands. It can be seen from Fig. 6 ͑ a ͒ that the subthreshold region is well modeled, which exhibits the ideal subthreshold swing of 60 mV/decade at room temperature ͑ at 100 K this is Ϸ 20 mV/decade). Below the threshold voltage the subbands are all above the Fermi level, but they are populated because the tail of the Fermi functions extend over them ͑ Fig. 3 ͒ . The difference between the transmitted tails of the source and drain Fermi functions explains, in the Landauer approach, the diffusion current, which is the dominant current in the subthreshold region. The linear extrapolated threshold voltage ͑ at low drain bias and T ϭ 300 K), ex- tracted from a linear I Ϫ V GS plot is about 330 mV for t Si ϭ 1.5 nm and 195 mV for t Si ϭ 3 nm. It is well predicted by our model even at very small silicon film thickness, where deviation from classical models is very important. The nanoMOS results are 320 and 185 mV, respectively. The off- current and on-current are also well captured by our model ͓ Fig. 6 ͑ a ͔͒ . For a detailed inspection of the on-current we have plotted in Fig. 6 ͑ b ͒ the I Ϫ V DS characteristic for a DG- MOSFET with a silicon film thickness of 1.5 nm working at room temperature. The departure on the characteristics predicted by the compact model with respect to the calculated ones by the nanoMOS simulator arises mainly from the number of subbands considered in both the compact model and nanoMOS simulator, the former dealing with one- dimensional subbands and the latter with two-dimensional subbands. For the nanoMOS calculations we have considered the maximum number of allowed subbands by the pro- gram; in the compact model a number exceeding one hun- dred. In this section we extend the DG-MOSFET compact model formulated in the above sections to the cylindrical GAA-MOSFET. The following modifications have to be in- corporated: ͑ i ͒ the intrinsic carrier concentration, given by Eq. ͑ A3 ͒ , has to be divided by the area of the circular section ( ␲ t Si 2 /4) instead of the area of the rectangular section ( Wt Si ); ͑ ii ͒ the separation between the bottom of the conduction band and the bottom of the subbands is given by the theory of the cylindrical quantum potential well ͑ see Appendix B ͒ ; ͑ iii ͒ the new oxide capacitance ͑ per unit area ͒ for the cylindrical geometry is given by C ox ox 2 ln ͑ 1 2 t ox / t Si ͒ , 15 ͑ iv ͒ the potential in the channel is a solution of the Poisson’s equation for the cylindrical geometry ͑ see Appendix C ͒ . The surface and center potentials appearing in Eqs. ͑ 7 ͒ and ͑ 9 ͒ must be modified in accordance with it; and ͑ v ͒ for the cylindrical geometry, there are two sets of valleys, the first one is four-fold degenerated with a density of states effective mass m 1 d ϭ m T , and the second set, two-fold degenerated, has a density of states effective mass m 2 d ϭ m L . In order to test our approach we have compared the results given by our compact model with an experiment reported in the literature. 19 The GAA-MOSFET of the experiment has a diameter ( t Si ) of 65 nm, the insulator is silicon oxide with a thickness of 35 nm. The work-function of the gate material has been fixed to 4.43 eV in the compact model to match the experimental threshold voltage ͑ 0.48 V ͒ . To observe one-dimensional subband effects for this size, the operation temperature was 70 mK. In Fig. 7 we compare the measured transconductance ͑ dotted line ͒ with the simulated results by the compact model ͑ solid line ͒ . The position of the five main peaks is well predicted by the compact model. A detailed analysis reveals eight subbands below E FS in the analyzed voltage range. When the gate voltage is large enough the subband bottom energy reaches E FD . Every time one subband crosses E FS ( E FD ) a positive ͑ negative ͒ peak on the transconductance is recorded. The transconductance step is given by the derivative of the subband bottom energy with respect to the gate voltage multiplied by 4 G 0 or 2 G 0 , depending whether the subband belongs to the first or second set of valleys, respectively. The need for compact models of nanoscale transistors is increasingly important for future development of computer- aided-design tools at the circuit level. In this work we have presented a physics-based model for the ballistic quantum wire and quantum well MOSFET, derived from the Landauer transmission theory. The main novelty is that it extends modeling concepts of quantum well MOSFETs, to structures of lower dimensionality ͑ quantum wire ͒ , and is easily adaptable to gate structures as the single-gate, double-gate, or gate-all- around. The proposed model works in all the operation regions, below and above threshold, for low and high temperatures, incorporating effects of multisubband conduction, and taking into account the band structure of silicon. To verify the model we have proposed numerical experiments compar- ing the results with self-consistent simulations. The quantum wire model was used to predict the transconductance structure of a real device, showing good agreement. The intrinsic carrier density is evaluated by integrating the product N 1 D ( E ) • f ( E ) over all the energies in the conduction band and summing for all the subbands and ...