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![Employed delay cell of [29] for ring oscillator block](publication/347846622/figure/fig7/AS:11431281178998523@1691144452033/Employed-delay-cell-of-29-for-ring-oscillator-block.png)
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![Conventional form of PFD‐CP [17] with corresponding waveforms
(a) Block...](publication/347846622/figure/fig2/AS:11431281178998501@1691144447269/Conventional-form-of-PFD-CP-17-with-corresponding-waveforms-a-Block-diagram-of_Q320.jpg)
In this study, the design routine of a novel phase frequency detector and charge‐pump (PFD‐CP) is discussed. The main advantage of the proposed circuit is its improved dead zone performance as the circuits of PFD‐CP have been merged to reduce the latency of the structure. To justify this, by means of a reconfigurable loop filter, a fast‐locking low...
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![Fig. 3 CMOS circuit of Charge Pump [4]](profile/Kruti-Thakore/publication/370690360/figure/fig2/AS:11431281157618256@1683870214452/CMOS-circuit-of-Charge-Pump-4_Q320.jpg)
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This paper presents a Low power charge pump, second order low pass filter and voltage controlled oscillator for low power phase lock loop. The paper contains the detailed circuit diagram of charge pump, loop filter and voltage control oscillator with 1.8v power supply. The design has been realized using 0.18um CMOS technology. Here current starved...
This study presents an inductance capacitance (LC) phase-locked loop (PLL) with a dual voltage-controlled oscillator (VCO) and a noise-reduced low-dropout (LDO) regulator, which was used in four-lane multiprotocol serial link applications. The dual VCO architecture can increase the total frequency-tuning range to ensure that the LC PLL achieves mul...
Based on the standard 40 nm Complementary Metal Oxide Semiconductor (CMOS) process, a curvature compensation technique is proposed. Two low-voltage, low-power, high-precision bandgap voltage reference circuits are designed at a 1.2 V power supply. By adding IPTAT (positive temperature coefficient current) and ICTAT (negative temperature coefficient...
The conventional active CG‐CS balun low‐noise amplifiers (LNAs) with asymmetric outputs exploit a relatively weak output balance, limited IIP2, and high power consumption. This study presents a wideband balun‐LNA with symmetrical outputs. The proposed LNA utilizes a symmetrical capacitive cross‐coupled (CCC) technique between active balun and resis...
This paper presents a high speed phase frequency detector with charge pump and second order loop filter for low jitter and low power phase lock loop. The high speed phase frequency detector with dead zone compensation has been proposed. The paper contains the detailed circuit diagram of PFD, charge pump and loop filter with 1.2v power supply, 2ps j...
Citations
... Modern wireless communication has increased the demand for the low power phase lock loop (PLL) based frequency synthesizer [1][2][3]. Low power PLL design is still a critical task for achieving the optimum performance such as phase noise, locking time, and stability [3][4][5][6]. A closed-loop feedback control system is referred to as a PLL that is depicted in Fig. 1 that includes phase frequency detector (PFD), Loop filter, voltage control oscillator (VCO), and frequency divider blocks. ...
... The control voltage ( V cont. ) can be supplied to the oscillator input to generate stable frequency (f out ) for the PLL as per Eq. (21) [2]. ...
The demand for the high-speed PLL has increased to fulfil the requirement of the present RF communication industry. This paper deals with the designing of a third-order Gm-C loop filter with improved PLL performance. The high gain and low power Operational transconductance amplifier (OTA) is the basic building block of the third order Gm-C filter. The proposed folded cascode (FC) OTA has designed using dynamic threshold MOS (DTMOS) type input differential stage to achieve the dc gain of 77.07 dB, UGB of 25.02 MHz and power consumption of 94.89 μW. The low power FC OTA design leads to the enhancement in the figure of merits for FOMS and FOML for the small-signal and large-signal operation that is given 4777.07 MHz.pF/mW and 3891.91 V.pF/μs.mW, respectively. Further, the third-order reconfigurable Gm-C filter has designed and achieved 25.02 MHz of the cut-off frequency. It consumes power of 283.66 μW at 1.8 V supply voltage that shows 8.44 % reduction in power as compared to state of the art work. The proposed Gm-C is attained --132.08 dBc/Hz phase noise at 1MHz offset that shows 21.62 dB reduction in the phase noise than the reported results. The locking time of approximately 0.34 μs has measured with the help of an analytical approach for the Integer-N PLL 5G applications. The transistor-level simulation has been done using 180 nm CMOS process.
With the development of high-speed low power integrated circuits, fast locking PLL based frequency synthesizer has huge demand. This work deals with the design of the low power and high-performance two-stage operational transconductance amplifier (OTA). A Gate-driven quasi floating gate (GD-QFG) technique has been incorporated to minimize the power consumption of the OTA. The proposed OTA has been simulated with the help of a 180 nm CMOS process at 1 V supply. The dc gain, unity-gain bandwidth (UGB), and power consumption have achieved 82.26 dB and 38.37 MHz and 189.55 µW, respectively. Further, the proposed low power OTA has been used for the designing of a high frequency second-order Gm-C filter. The cut-off frequency and third-order intermodulation (IIP3) of the Gm-C filter is 9.15 MHz, and –3.17 dm respectively. The power consumption is 340 µW at the 1 V voltage supply. The proposed Gm-C filter can be utilized for fast-locking PLL based frequency synthesizer.KeywordsCMOSOTAGD-QFG MOSSecord-order Gm-C filter
High-speed PLL is highly demanding with the advancement in the VLSI market. PLL performance gets affected due to bandwidth limitation. This paper presents third-order configurable transconductance capacitance ([Formula: see text]-[Formula: see text])-based loop filter for high-speed PLL. Operational transconductance amplifier (OTA) serves as a basic cell of the [Formula: see text]-[Formula: see text] filter. Quasi-floating gate (QFG) and Bulk-driven qausi-floating gate (BD-QFG) MOS-based differential input folded cascode (FC) OTAs are proposed for low-voltage operation. Here, DC gain of the BD-QFG FC OTA enhanced 5.18% than QFG FC OTA. The proposed OTAs enhanced DC gain, CMRR, UGB and FOM along with reduction in the power consumption in comparison to the state-of-art work. Further, third-order [Formula: see text]-[Formula: see text] filters are designed using both QFG and BD-QFG MOS-based OTAs and achieved [Formula: see text]3[Formula: see text]dB cut-off frequency of 16.51[Formula: see text]MHz and 17.22[Formula: see text]MHz, respectively. The proposed QFG and BD-QFG MOS-based filters achieved 22.42% and 21.53% reduction in power than the reported result, respectively. The locking time of integer-N PLL is calculated as 0.33[Formula: see text][Formula: see text]s and 0.32[Formula: see text][Formula: see text]s, respectively, through an analytical approach. The transistor-level simulation has been done in 0.18[Formula: see text][Formula: see text]m CMOS process.
A wide range frequency synthesizer is designed with the help of dual voltage tunable Differential Ring Oscillator (DRO). Frequency ranging from 534[Formula: see text]MHz to 18.56[Formula: see text]GHz can be generated using the proposed synthesizer. As proposed circuit utilizes dual voltage tunable DRO, a select input is provided to control the output frequency range. Logic low value (0[Formula: see text]V) of select input generates frequencies from 534[Formula: see text]MHz to 5.08[Formula: see text]GHz whereas logic high value (1.1[Formula: see text]V) of select input enables the frequency generation in the range of 5.08[Formula: see text]GHz to 18.56[Formula: see text]GHz. This work utilizes a single charge pump and single loop filter along with charge pump and bias control circuit. Proposed circuit is designed in GPDK 45-nm CMOS technology with supply voltage of 1.1[Formula: see text]V. Power consumption of the proposed circuits is 2.88[Formula: see text]mW while generating frequency of 7.84[Formula: see text]GHz. Proposed synthesizer demonstrates Figure of Merit (FoM2) of [Formula: see text][Formula: see text]dBc/Hz at this frequency. Because of such a wide spectrum, this synthesizer is well suited in the field of satellite communication, GPS and navigation.
