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![Effects of number of transitions on the TDC precision. [3]](profile/Cahit-Ugur/publication/258309820/figure/fig1/AS:650407294545922@1532080591499/Effects-of-number-of-transitions-on-the-TDC-precision-3.png)
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![Figure 1. Effects of number of transitions on the TDC precision. [3]](profile/Cahit-Ugur/publication/258309820/figure/fig1/AS:650407294545922@1532080591499/Effects-of-number-of-transitions-on-the-TDC-precision-3_Q320.jpg)
One of the most important aspects of particle identification experiments
is the digitisation of time, amplitude and charge data from detectors.
These conversions are mostly undertaken with Application Specific
Integrated Circuits (ASICs). However, recent developments in Field
Programmable Gate Array (FPGA) technology allow us to use commercial
elec...
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IGBT, field programmable gate array (FPGA), switching losses, high power discrete device, converter control, Efficiency Improving the performance of prospective inverters can not only be realised by advanced power semiconductors and faster signal-processing components on its own. Even the circuitry that combines all together opens up new possibilit...
Citations
... Also, since the individual delays in the delay line are not identical to each other, they need to be calibrated before use. With a properly calibrated delay line and with a stable clock signal for all input channels, a time precision of the order of 10 ps RMS can be achieved [187][188][189][190][191]. ...
PUMA, antiProton Unstable Matter Annihilation, is a nuclear-physics experiment at CERN aiming at probing the surface properties of stable and rare isotopes by use of low-energy antiprotons. Low-energy antiprotons offer a very unique sensitivity to the neutron and proton densities at the annihilation site, i.e. in the tail of the nuclear density. Today, no facility provides a collider of low-energy radioactive ions and low-energy antiprotons: while not being a collider experiment, PUMA aims at transporting one billion antiprotons from ELENA, the Extra-Low-ENergy Antiproton ring, to ISOLDE, the rare-isotope beam facility of CERN. PUMA will enable the capture of low-energy antiprotons by short-lived nuclei and the measurement of the emitted radiations. In this way, PUMA will give access to the so-far largely unexplored isospin composition of the nuclear-radial-density tail of radioactive nuclei. The motivations, concept and current status of the PUMA experiment are presented.
... The TRB3 is capable of a time precision better than 10 ps and it can be reprogrammed to improve the performance down to few ps if fewer channels are needed [45]. It is worth noting that some prototypes were tested [46] where an FPGA was also used as discriminator. The extreme flexibility of this solution came with a small cost in terms of performance, but still had a time precision better than 25 ps. ...
Timing detectors are a well-established part of High Energy Physics experimental instrumentation. The choice of sensors with fast (less than 10 ns) and precise (better than 100 ps) signals, together with radiation resistance considerations, are an essential part of the design of a timing detector. In this paper, the main characteristics that make single diamond crystal sensors ideal for timing applications will be described and an introduction to the design of fast front-end electronics will be given. Finally, two examples of diamond timing detectors used in High Energy Physics, the START detector of HADES and the TOTEM/CMS timing detector, will be discussed.
... The sensors are read out by an updated version of the trigger and readout board (TRB) [14], developed for the high-acceptance dielectron spectrometer (HADES) experiment [15], in combination with the PADIWA front-end amplification and discrimination card [16], mounted directly on the MCP-PMTs. This FPGA-based system provides measurements of both the photon arrival time and time-over-threshold (TOT), which is related to the pulse height of the analog signal and can be used to monitor the sensor performance and to perform time-walk corrections to achieve the required precision of the photon timing. ...
... The sensors are read out by an updated version of the trigger and readout board (TRB) [14], developed for the high-acceptance dielectron spectrometer (HADES) experiment [15], in combination with the PADIWA front-end amplification and discrimination card [16], mounted directly on the MCP-PMTs. This FPGA-based system provides measurements of both the photon arrival time and time-over-threshold (TOT), which is related to the pulse height of the analog signal and can be used to monitor the sensor performance and to perform time-walk corrections to achieve the required precision of the photon timing. ...
The (anti-Proton ANnihiliation at DArmstadt) experiment will be one of the four flagship experiments at the new international accelerator complex FAIR (Facility for Antiproton and Ion Research) in Darmstadt, Germany. will address fundamental questions of hadron physics and quantum chromodynamics using high-intensity cooled antiproton beams with momenta between 1.5 and 15 GeV/c and a design luminosity of up to 2 × 10³² cm⁻² s⁻¹. Excellent particle identification (PID) is crucial to the success of the physics program. Hadronic PID in the barrel region of the target spectrometer will be performed by a fast and compact Cherenkov counter using the detection of internally reflected Cherenkov light (DIRC) technology. It is designed to cover the polar angle range from 22° to 140° and will provide at least 3 standard deviations (s.d.) π/K separation up to 3.5 GeV/c, matching the expected upper limit of the final state kaon momentum distribution from simulation. This documents describes the technical design and the expected performance of the Barrel DIRC detector. The design is based on the successful BaBar DIRC with several key improvements. The performance and system cost were optimized in detailed detector simulations and validated with full system prototypes using particle beams at GSI and CERN. The final design meets or exceeds the PID goal of clean π/K separation with at least 3 s.d. over the entire phase space of charged kaons in the Barrel DIRC.
... Then, FPGA-based digitization was developed with TDCs and FPGA built-in LVDS buffers intentionally used as internal comparators [10]. Moreover, programmable logic now provides a fast sampling scheme that may also be refined towards a single-slope ADC with additional hardware [11][12][13]. ...
This work shows a time-domain method for the discrimination and digitization of parameters of voltage pulses coming from optical detectors, taking into account the presence of electronic noise and afterpulsing. Our scheme is based on an FPGA-based time-to-digital converter as well as an adjustable-threshold comparator complemented with commercial elements. Here, the design, implementation and optimization of a
multiphase TDC using delay lines shorter than a single clock period is also described. The performance ofthis signal processing system is discussed through the results from the statistical code density test, statistical distributions of measurements and information gathered from an optical detector. Unlike dual voltage threshold discriminators or constant-fraction discriminators, the proposed method uses amplitude and time information to define an adjustable discrimination window that enables the acquisition of spectra.
... To make it possible, several schemes have been developed, such as time-to-amplitude converters [2], constantfraction discriminators [3], simplified schemes of lock-in amplifiers [4], and time-over-threshold discrimination [5]. This last scheme allows a flexible development of a TDC and usage of device builtin LVDS buffers intentionally used as comparators [6]. Moreover, this scheme can use a ramp generator to make a single-slope ADC. ...
... The output current pulse was preamplified with a Mini-circuits ZX60-P103LN+ module. Then, a LVDS buffer, used intentionally as a comparator, makes a digital representation of the pulse [6][7]. The noninverting output receives the measure signal, whereas the inverting output receives a voltage threshold adjusted by a digital-to-analogue converter (MAX5825, 1 resolution). ...
... The CCD sensor (Toshiba TCD1304AP) from the spectrometer has a sensitivity range from 200 to 1100 . This allows the detection of the spectral line around 312. 6 in the CCD sensor. For position, the most similar spectral lines are around 546 , and the 577 and 579 pair, respectively. ...
This work shows a time-domain method for the discrimination and digitization of pulses coming from optical detectors, considering the presence of electronic noise and afterpulsing. The developed signal processing scheme is based on a time-to-digital converter (TDC) and a voltage discriminator. After setting appropriate parameters for taking spectra, acquisition data was corrected by wavelength, intensity response function, and noise suppression. The performance of this scheme is discussed by its characterization as well as the comparison of its spectra to those obtained by an Ocean Optics HR4000 commercial reference.
... The FPGA based control system performs in an equivalent manner to bus-based architecture such as VME, PXI with the addedbenefit of lower cost per channel. The FPGA works on digital data only; the analog to digital converter (ADC), digital to analog converter (DAC) are integrated on one printed circuit board (PCB) along with digital clock manager of FPGA which works as a stand-alone portable control and data acquisition system in any type of real world applications [6]. The micro-controller is used in slow control system (∼ 1µsec) with the requirement of less numbers of channels. ...
For reliable and uninterrupted operation of Thomson
scattering diagnostic, a reliable, simple and distributed control system is
developed. The use of Field Programmable Gate Array (FPGA) based stand-alone
control system, rugged PXI based timing system, simple digital input-output
controller using micro-controller, USB based oscilloscope and Ethernet based
data communication for client-server architecture makes the control system
to operate in an effective manner. The LabVIEW based software architecture
controls and monitors the action in a more simple and transparent manner.
The developed control system is modular in terms ofup gradation, flexibility
and redundant facility.
... For this platform various front-end electronics (FEE) were developed and are being developed for Time-of-Flight (ToF), Time-over-Threshold (ToT) and charge measurements. One low cost FEE developed for the ToF and ToT measurements of a MCP detector for the PANDA experiment uses an FPGA for setting the thresholds and the internal LVDS buffers for signal discrimination [12]. With this setup a time precision of ∼ 17 ps RMS is achieved. ...
In this paper the implementation of a 65 channel high precision Time-to-Digital Converter in a single Field Programmable Gate Array (FPGA) is presented. The TDC applies the interpolation method for time measurements. The precision of the TDC is increased with the Wave Union Launcher method. In order to overcome the minimum pulse width limitation a semi-asynchronous pulse stretcher is implemented which has been verified to allow a measurement of a pulse width < 500 ps. The TDC has a typical precision of 7.2 ps RMS (14 ps RMS on the worst channel) on a single channel. Additionally, the 264 Channel TDC Platform, TDC Readout Board (TRB3), is presented in the paper applying the described TDC.
... Owing to its flexible design, an application-specific trade-off between number of channels, time precision and dead-time can be achieved for each front-end design. Implementation details can be found in [2] and first applications are described in [3]. The TRB3 firmwares as part of the HADES experiment use the TrbNet [4] for asynchronous readout and busy-release scheme trigger distribution. ...
... wide-band amplifiers) and RC low-pass filters are used to generate the threshold voltages via pulsewidth modulation. Using test pulses with an amplitude of 500 µV and a length of 6 ns, a time precision of the full system including the TRB3 of 23 ps was measured [3]. This front-end has been successfully used in beamtimes, see sections 5 and 6. ...
The TRB3 features four FPGA-based TDCs with < 20 ps RMS time precision between two channels and 256+4+4 channels in total. One central FPGA provides flexible trigger functionality and GbE connectivity including powerful slow control. We present recent users' applications of this platform following the COME&KISS principle:
successful test beamtimes at CERN (CBM), in Jülich and Mainz with an FPGA-based discriminator board (PaDiWa), a charge-to-width FEE board with high dynamic range, read-out of the n-XYTER ASIC and software for data unpacking and TDC calibration in ROOT. We conclude with an outlook on future developments.
... These AddOns can carry all detector dependent electronics ranging from basic adaptor boards to many-channel ADC boards or additional optical links. More details on this approach can be found in [4]. ...
Virtually all Data Acquisition Systems (DAQ) for nuclear and particle physics experiments use a large number of Field Programmable Gate Arrays (FPGAs) for data transport and more complex tasks as pattern recognition and data reduction. All these FPGAs in a large system have to share a common state like a trigger number or an epoch counter to keep the system synchronized for a consistent event/epoch building. Additionally, the collected data has to be transported with high bandwidth, optionally via the ubiquitous Ethernet protocol. Furthermore, the FPGAs' internal states and configuration memories have to be accessed for control and monitoring purposes.
Another requirement for a modern DAQ-network is the fault-tolerance for intermittent data errors in the form of automatic retransmission of faulty data. As FPGAs suffer from Single Event Effects when exposed to ionizing particles, the system has to deal with failing FPGAs. The TrbNet protocol was developed taking all these requirements into account. Three virtual channels are merged on one physical medium: The trigger/epoch information is transported with the highest priority. The data channel is second in the priority order, while the control channel is the last. Combined with a small frame size of 80 bit this guarantees a low latency data transport: A system with 100 front-ends can be built with a one-way latency of 2.2 us.
The TrbNet-protocol was implemented in each of the 550 FPGAs of the HADES upgrade project and has been successfully used during the Au+Au campaign in April 2012. With 2⋅10⁶/s Au-ions and 3% interaction ratio the accepted trigger rate is 10 kHz while data is written to storage with 150 MBytes/s. Errors are reliably mitigated via the implemented retransmission of packets and auto-shut-down of individual links. TrbNet was also used for full monitoring of the FEE status. The network stack is written in VHDL and was successfully deployed on various Lattice and Xilinx devices. The TrbNet is also used in other experiments, like systems for detector and electronics development for PANDA and CBM at FAIR. As a platform for such set-ups, e.g. for high-channel time measurement with 15 ps resolution, a generic FPGA platform (TRB3) has been developed.
