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Electronic Stacked integrated circuits presents many advantages like short latency, low power consumption, and immense amount of bandwidth delivered by Through Silicon Vias (TSV). However, these circuits present many test issues, designer must ensure that each of individual die layer is designed to be testable before bonding take places. In this pa...
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Complex radix (−1+j) allows the arithmetic operations of complex numbers to be done without treating the divide and conquer rules, which offers the significant speed improvement of complex numbers computation circuitry. Design and hardware implementation of complex radix (−1+j) converter has been introduced in this paper. Extensive simulation resul...
Citations
... If the faulty stacked dies are identified, then the remaining dies will not be used. The outgoing product quality is guaranteed by the final test [16]. Performing all these tests allows the manufacturer to distinguish the functional circuits from the failed ones. ...
Through silicon via (TSV) is established as the main enabler for 3D IC that
increases system density and compactness. The exponential increase in TSV density led
to TSV-induced catastrophic and parametric faults. We propose an original architecture
that detects errors caused by TSV manufacturing defects. The proposed DFT is a built-
in technique that detects errors in an early manufacturing stage, hence very
economically attractive. The proposal is capable of testing each and every TSV in the
network. The technique achieves a high fault coverage and a high observability.
... Techniques designed to test analog and mixed signal circuits in Complementary metal-oxide-semiconductor (CMOS) technology are not as mastered and developed as techniques designed to test digital ones [1] [2]. In analog circuits there are several parameters to test. ...
In this paper we evaluate the effectiveness of current monitoring techniques in detecting Bridge and open defects in CMOS operational amplifiers. We evaluate the detection capabilities by using two current testing techniques. The first technique consists in the oversight of the transient supply current (IDDT) and the second technique consists in the monitoring of quiescent supply current (IDDQ). The most likely resistive and open defects are injected using fault injection additional transistors. Performances of the CMOS operational amplifier are also evaluated after each fault injection. Spice simulations were realized to compare the proposed test techniques and evaluate the best performing one.
... This new design uses more surface and material resources but offers more reliability (Figure 3). However, other types of defects can decrease current consumption (Guibane, Hamdi, & Mtibaa 2016). A BICS with dual current mirror is designed in (Guibane, Hamdi & Mtibaa 2016). ...
... However, other types of defects can decrease current consumption (Guibane, Hamdi, & Mtibaa 2016). A BICS with dual current mirror is designed in (Guibane, Hamdi & Mtibaa 2016). With this BICS, we can define 2 currents references. ...
... If out1 and out 2 are in the low state, General output of the BICS Gout is set to 0, indicating absence of defects. The NMOS transistor Q0 is used as a switch to isolate or connect the CUT to the BICS (Guibane, Hamdi, & Mtibaa 2016). Injection of 2 permanent defects (defect 1 and defect 2) Figure 11 shows the behaviour of the system with the injection of 2 permanent defects (defect 1 and defect 2 respectively at the first and the second amplifier). ...
Off line test is essential to ensure good manufacturing quality. However for permanent or transient faults that occur during the use of the integrated circuit in an application, an online integrated test is needed as well. This procedure should ensure the detection and possibly the correction or the masking of these faults. This requirement of self-correction is sometimes necessary, especially in critical applications that require high security such as automotive, space or biomedical applications. We propose a fault tolerant design for analogue and mixed-signal design CMOS circuits based on IDDQ testing. A defect can cause an increase in current consumption. IDDQ testing technique is based on the measurement of power supply current to distinguish between functional and failed circuits. The technique has been an effective testing method for detecting physical defects such as gate-oxide shorts, floating gates (open) and bridging defects in CMOS integrated circuits. An architecture called BICS (Built In Current Sensor) is used for monitoring the supply current (IDDQ) of the connected integrated circuit. If the measured current is not within the normal range, a defect is signalled and the system switches connection from the defective to a functional integrated circuit. The fault tolerant technique is composed essentially by a double mirror built-in current sensor, allowing the detection of abnormal current consumption and blocks allowing the connection to redundant circuits, if a defect occurs. Spices simulations are performed to valid the proposed design.
