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Dual-rail SERT D-type flip flop.  

Dual-rail SERT D-type flip flop.  

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Fig. 1. TMR flip flop.  
Fig. 2. Half transition NAND gate and symbol.  
Fig. 3. SERT latch.  
Fig. 4. Dual-rail SERT D-type flip flop.  
+5 Fig. 5. Relative layout area of experiment blocks.  
Fault Tolerant FPGA Reconfigurable Hardware Architecture
Conference Paper
Full-text available
  • Sep 2008
FPGA architectures for fault tolerance typically support either built-in hardware redundancy, or firmware configurable redundancy. The configurable redundancy allows more flexibility in allocating resources, but is inefficient and burdens the development cycle. This paper presents a method whereby an FPGA or other programmable array device (e.g. mu...
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Context 1
... D-type dual-rail flip flop consists of two SERT latches, dual clock buffers between, and the usual data and inverted clear input logic as shown in Fig. 4. ...
Context 2
... errors. Within D-type flip flops, the clock for the slave latch (second half) is derived locally by inversion from the main clock, and is suscep- tible to SET in the single string circuits. Dual clocks are used within dual flip flops, where the clock for the second half of the cell is derived via inversion of the main clock as shown in Fig. 4. TMR flip flops triplicate the inverted second half ...

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