Figure 3 - uploaded by Zeynep Kaya
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Dual port memory block diagram illustrates that the same memory block can be addressed by two ports independently. Conflicts occur when one port try to write at the same address the other port is writing/reading.
Contexts in source publication
Context 1
... are especially useful in the projects with stringent real-time requirements. A dual port memory block can be modeled as illustrated in Figure 3. Dual port memory blocks usually have different operating modes for different requirements of the application. ...
Context 2
... are especially useful in the projects with stringent real-time requirements. A dual port memory block can be modeled as illustrated in Figure 3. Dual port memory blocks usually have different operating modes for different requirements of the application. ...
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In this work, the quantum version of 3D FFT is proposed for constructing velocity filters. Velocity filters are desirable when we need to separate moving objects with a specific velocity range in amplitude and direction in a rapidly changing background. These filters are useful in many application fields, such as for monitoring regions for security...
Citations
... There are a few single-block dual-port memory-based FFT architectures that use memory size equal to FFT size in the literature (Seke and Kaya, 2018). Therefore, the contribution of our approach is a cost-beneficial procedure for optimizing memory usage (N) as well as providing and uncomplicated design. ...
Purpose-This paper aims to present a single-block memory-based FFT processor design with a conflict-free addressing scheme for field-programmable gate arrays FPGAs with dual-port block memories. This study aims for a single-block dual-port memory-based N-point radix-2 FFT design that uses memory locations and spending minimum clock cycle. Design/methodology/approach-A new memory-based Fast Fourier Transform (FFT) design that uses a dual-port memory block is proposed. Dual-port memory allows the design to perform two memory reads and writes in a single clock cycle. This approach achieves low operational clock and smallest memory simultaneously, excluding some small overhead for exceptional address changes. The methodology is to read from while writing to a memory location, eliminating the need for excess memory and additional clock cycles. Findings-With the minimum memory size and the simplest architecture, radix-2 FFT and single-memory block are used. The number of clock pulses spent for all FFT operations does not provide much advantage for low-point FFT operations but is important for high-point FFT operations. With the developed algorithm, N memory is used, and the number of clock pulses spent for all FFT stages is (N/2 11)log2N for all FFT operations. Originality/value-This is an original paper, which has simultaneously in whole or in part been submitted anywhere else.
Purpose
This paper aims to present a single-block memory-based FFT processor design with a conflict-free addressing scheme for field-programmable gate arrays FPGAs with dual-port block memories. This study aims for a single-block dual-port memory-based N-point radix-2 FFT design that uses memory locations and spending minimum clock cycle.
Design/methodology/approach
A new memory-based Fast Fourier Transform (FFT) design that uses a dual-port memory block is proposed. Dual-port memory allows the design to perform two memory reads and writes in a single clock cycle. This approach achieves low operational clock and smallest memory simultaneously, excluding some small overhead for exceptional address changes. The methodology is to read from while writing to a memory location, eliminating the need for excess memory and additional clock cycles.
Findings
With the minimum memory size and the simplest architecture, radix-2 FFT and single-memory block are used. The number of clock pulses spent for all FFT operations does not provide much advantage for low-point FFT operations but is important for high-point FFT operations. With the developed algorithm, N memory is used, and the number of clock pulses spent for all FFT stages is (N/2 +1)log2N for all FFT operations.
Originality/value
This is an original paper, which has simultaneously in whole or in part been submitted anywhere else.
