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This paper presents a wide operation range 0.18mum CMOS frequency divider for 60GHz wireless applications. The direct injection lock technique is used to perform the signal division at millimeter-wave frequency. The deep n-well is implemented under the NMOS switch transistor to improve the lock range of the frequency divider. Combined with band swi...
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... paper presents a wide operation range 0.18m CMOS frequency divider for the 60GHz dual-conversion zero-IF receiver architecture as shown in Fig. 1. The dual- conversion instead of the popular direct-conversion receiver architecture is chosen to relax the requirement of local oscillator and mixers. The 48GHz local oscillator (LO) used for the first stage down-conversion is feasible in the commercial 0.18m CMOS technology [1]. To reduce the component count and avoid mutual coupling ...
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Citations
... Majority of the published high frequency (above 30 GHz) ILFDs, either based on conventional [3] or direct-injection [4] ...
... Due to the input matching technique, the input power of -38 dBm is lower than the designs in [4- 5][7]. As the only quadrature divider in the table, the power consumption is comparable to non-quadrature designs in [4]- [5]. The measured phase noise is also lower than all cited works in Table I. ...
This paper presents a wideband 40 GHz divide-by-2 quadrature injection locked frequency divider (Q-ILFD) as an enabling component for sliding-IF 60 GHz transceivers. The design incorporates direct injection topology and input power matching using interconnect inductances to enhance injection efficiency. This results in an excellent input sensitivity and a wide locking range. Fabricated in a 65 nm bulk CMOS technology, the divider operates from 30.3 to 44 GHz (37% locking range) while consuming 9 mW from a 1.2 V supply. The measured phase noise is -131 dBc/Hz at 1-MHz offset whereas the phase error between I-Q outputs is less than 1.44°.
... The digital implementation of frequency dividers is based on flip-flop logic circuits [11]–[12]. The analog implementation of frequency dividers includes ring-oscillator-based injection locking [13][14], frequency regeneration [15]–[16], and resonator-based injection locking [17]–[18]. The flip-flop-based frequency dividers have the advantages of wide locking range and various division ratios, but usually suffer from high power consumption and low operation frequency. ...
... Thus, in a manner similar to a single-balanced mixer, M 1 and M 2 translate the input to f in ± f in /2, injecting the result into the tanks. This translation is accompanied by a conversion factor of 2/π [17] if the cross-coupled pair switches abruptly and the capacitance at node P is neglected. As a result, the current injected into the tank at f in /2 has a peak value of (2/π) @BULLET I inj , allowing to find an expression for the locking range of the oscillator inFig. ...
In this paper, an Injection Locking Frequency Divider (ILFD) in 65 nm RF CMOS Technology for applications in millimeter-wave (mm-W) band is presented. The proposed circuit achieves 12.69% of locking range without any tuning mechanism and it can cover the entire mm-W band in presence of Process, Voltage and Temperature (PVT) variations by changing the Injection Locking Oscillator (ILO) voltage control. A design methodology flow is proposed for ILFD design and an overview regarding CMOS capabilities and opportunities for mm-W transceiver implementation is also exposed. Postprint (published version)
... To clearly show the trade-off between them, curves of Q min versus tuning range γ, once again, are plotted in So, tuning range can be traded off for high-Q performance in SDR varactors. For example, such varactors can be used in a dual-conversion receiver [Li03] operating around 50 GHz [Che06,Luo05]. The incoming signal is down-converted twice by using two VCOs. ...
This paper presents a low power 44 GHz 0.18 μm CMOS superharmonic frequency divider. The superharmonic locking technique is proposed to perform direct divide-by-four operation. The integrated circuit was implemented in the commercial 0.18 μm CMOS technology. Operated at 1.2 V, the frequency divider consumes only 1.8 mW of power. The measured locking range of the frequency divider is 200 MHz. By applying varactor tuning, the operating range of the divider can be extended to 2.14 GHz. The chip occupied 0.77 mm × 0.8 mm of silicon area including the testing pads.
A K-band low-power and wideband injection-locked frequency divider (ILFD) using 0.18-μm CMOS technology is presented in this paper. To achieve the wide-locking-range and low-power consumption, the inductive peaking and current-reused techniques are adopted. The measurement results show that the proposed ILFD has a locking range of 5.5 GHz (23.6%), from 20.5 to 26 GHz, at the incident power of 0 dBm, with a very low power consumption of 1.5 mW. Among 180 nm and 130 nm CMOS frequency dividers, the proposed ILFD achieves wide locking range with the lowest dc power and RF injected power at K-band.
A 58-GHz (V-band) CMOS direct injection-locked frequency-divider (DILFD) using input-power-matching technique for locking-range enhancement is reported for the first time. In an input-power-matching technique, an inductive input-matching-network is added to the gate of the NMOS switch to optimize the input-power-matching, i.e. to maximize the internal power, over the frequency band of interest. This DILFD architecture also features a very low input capacitance; therefore, high operating frequency of 58.2 GHz can be achieved. The DILFD dissipated 8.45 mW power from a 1.3 V power supply, and achieved a total locking range of 9.3 GHz (48.9-58.2 GHz; 17.4%), which is 400% higher than that (1.86 GHz (3%)) of a traditional DILFD without the input-matching-network for comparison. The chip area was only 0.585times0.492 mm2 excluding the test pads.
A 53–67 GHz wide locking range injection-locked frequency divider (ILFD) has been designed and fabricated using 0.13-μm CMOS process.By using forward body bias technique, the proposed ILFD demonstrates good performance of the wide locking range while maintaining low DC power consumption. Via a 0 dBm incident signal power, an input locking rage greater than 14 GHz (>23%) is achieved with 4 mW from supply voltage of 0.8 V. If the supply voltage further reduces to 0.6 V, the input locking rage is 6 GHz (10%) while consuming only 1.2 mW. Compared to previous reported works in high-speed CMOS FD, the presented ILFD achieves superior figure of merit (FOM). Without extra voltage control mechanisms to increase the locking range, this FD covers whole 57–64 GHz band is suitable for integration into a 60 GHz WPAN phase-locked loop system. © 2011 Wiley Periodicals, Inc. Microwave Opt Technol Lett 53:1386–1389, 2011; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.25989
A low-power and wide-locking-range 55.8-GHz (V-band) injection-locked frequency-divider (ILFD) using standard 0.13 μm CMOS technology is reported. To enhance locking range, a shunt inductor was introduced in the source node of the cross-coupled pair to maximize the equivalent load impedance of the tail transistor, i.e. to maximize the internal power, over the frequency band of interest. In addition, the inductors and capacitors of the LC-tank were implemented by low-Q micro-stripline inductors and high-Q varactors, respectively, to further improve the locking range of the ILFD. The result shows that a wide-locking-range of 7.1 GHz (from 48.7 GHz to 55.8 GHz, 13.6%) was achieved. The power consumption of the ILFD is only 2 mW from a 1.1 V power supply. The chip area was only 0.66 × 0.48 mm2 excluding the test pads. © 2009 Wiley Periodicals, Inc. Microwave Opt Technol Lett 51: 702–706, 2009; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.24148
A 58-GHz (V-band) CMOS direct injection-locked frequency-divider (DILFD) using input-power-matching technique for locking-range enhancement is reported for the first time. In an input-power-matching technique, an inductive input-matching-network is added to the gate of the NMOS switch to optimize the input-power-matching, i.e. to maximize the internal power, over the frequency band of interest. This DILFD architecture also features a very low input capacitance; therefore, high operating frequency of 58.2 GHz can be achieved. The DILFD dissipated 8.45 mW power from a 1.3 V power supply, and achieved a total locking range of 9.3 GHz (48.9–58.2 GHz; 17.4%), which is 400% higher than that (1.86 GHz (3%)) of a traditional DILFD without the input-matching-network for comparison. The chip area was only 0.585 × 0.492 mm2 excluding the test pads. © 2009 Wiley Periodicals, Inc. Microwave Opt Technol Lett 51: 685–689, 2009; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.24158
This letter presents the first RF frequency divider on glass to demonstrate the feasibility of system on display (SoD). The frequency divider is developed in 1P2M 3 mum low-temperature polycrystalline silicon (LTPS) thin-film transistor technology. The core cell of the LTPS direct injection-locked frequency divider is the single stage ring oscillator. The additional cross-coupled transistor pair increases the phase shift of the ring oscillator to meet the oscillation condition. The maximum locking range of the LTPS frequency divider is 2 MHz, and it can be operated from 120 Hz to 8 MHz with frequency tuning. Operated at 10 V, the frequency divider consumes 1.8 mW of power. The area of the frequency divider circuitry is 2.13 times 2.6 mm.
