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Drain current vs. the gate voltage overdrive for short and narrow nMOS on SOl and XsSOI along different orientations.
Source publication
We integrated Fully Depleted Silicon-On-Insulator (FDSOI) n and pMOSFETs on (1.16 percent, 2.1GPa) eXtremely strained SOI (XsSOI) substrates. We demonstrate a 135% electron mobility enhancement at W=77 nm and a significant I<sub>ON</sub>-I<sub>OFF</sub> improvement for short and narrow nMOS on XsSOI compared to unstrained SOI. We in-depth analyze t...
Contexts in source publication
Context 1
... the contrary, for wide and short nMOS oriented along <110>, a 13% (respectively 25%) performance improvement is observed on Figure 3 for sSOI (respectively XsSO!). This improvement is conserved for narrow and short channel devices (see Figure 4). To better understand the narrow channel behaviour, we plotted the effective mobility as a function of the effective gate width in Figure 5 for <11O>-oriented n and pMOS. ...
Context 2
... anisotropy under strain. These phenomena explain well that for narrow sSOI devices, where the tensile strain along the transport direction is dominant, i) the piezoelectric model underestimates the electron mobility ( Figure 11) and ii) the device performance is anisotropic with a better direction along <110> (Figure 7 and 4). Finally, in our devices, the active length (distance gate/contact) is higher than 0.3I1m. ...
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Citations
... Carrier mobility improvement is also needed for advanced nodes in order to further extend device performances, and many strain engineering solutions have been proposed in this way. The use of tensilestrained silicon-on-insulator (sSOI) substrates is very effective to improve the carrier mobility of n-MOSFETs, without any degradation for p-MOSFETs [3]. Alternative approaches for p-type devices on bulk Si and partially depleted SOI consist of the use of compressive contact etch stop layers [4] , different channel/substrate orientations [5], and embedded silicon– germanium (eSiGe) S/D [6]. ...
... 4 as a function of effective gate length. In agreement with literature results [3], we find that, for long devices, the hole low field mobility in sSOI is similar to the SOI one (μ 0 = 120 cm 2 · V −1 · s −1 ). Indeed, sSOI with classical Si S/D enables strongly boosting nMOS without any significant pMOS degradation. ...
Strained p-MOSFETs with recessed and embedded silicon-germanium (eSiGe) source/drain (S/D) are fabricated on either silicon-on-insulator (SOI) or strained SOI (sSOI) substrates of 15-nm body thickness. For a gate voltage overdrive of -1 V and a gate length L of 60 nm, p-MOSFETs on SOI (sSOI) with eSiGe exhibit a 37% (18%) saturation drive current enhancement compared to standard sSOI structures with Si S/D. The low field mobility and series resistance are extracted in order to understand the performance boost induced by the eSiGe process. The significant I_ON improvement of SOI pMOS with eSiGe S/D compared to sSOI pMOS with Si S/D is attributed to a 65% mobility enhancement and to a 30% series-resistance reduction with respect to sSOI pMOS with Si S/D at L = 60 nm.
In the first part of this two-part article, implant-induced strain relaxation has been successfully demonstrated on a common strained silicon-on-insulator (SSOI) platform. In this second part, based on an SSOI platform that could enable the cointegration of highly tensile-strained Si n-channel field-effect transistors (nFETs) and compressive-strained SiGe p-channel FETs (pFETs) on the same substrate for both logic and 5G RF circuits, we here propose a comb-like device structure within the strained SOI platform for further improvement in the electrostatic, dc, and RF performances over the unstrained SOI FinFETs counterpart. It is demonstrated that the peak
${G}_{\text {m}}$
of strained comb-like Si nFETs can be improved by 35% over unstrained n-type FinFETs SOI. The improvements of
${f}_{\text {T}}$
by 22% and
${f}_{\text {max}}$
by 36% over no-comb devices are also observed. Furthermore, the linearity of
${f}_{\text {T}}$
and
${f}_{\text {max}}$
has been greatly improved by introducing forward body biasing on the comb-like device structure.
Strained silicon-on-insulator (SSOI) is a promising platform for 5G, which will require both high-performance and low-power complementary metal–oxide–semiconductor (CMOS) devices. Hence, it is important to understand the behavior of strain in SSOI at deeply scaled dimensions. We thus present a simulation study of SSOI technology, where the strain profiles of “fins” with different dimensions and layer thicknesses are analyzed. We discover, for the first time, that a buried oxide (BOX) as thin as 10–15 nm is able to effectively memorize the strain. It is also able to retain the strain under annealing up to 1000 °C, a result verified by the Raman measurements. Such a thin BOX enables a good back-gate control for dynamic threshold voltage (
${V}_{\text{t}}$
) tuning of SSOI transistors. The ability to have a good performance enhancement (from strain), and dynamic
${V}_{\text{t}}$
tunability (from thin BOX) makes SSOI favorable for 5G mixed-signal applications.
IntroductionImpact of Strain on the Electronic Properties of SiliconMethods to Generate Strain in Silicon DevicesStrain Engineering for 22 nm CMOS Technologies and BelowConclusions
References
The use of mechanical stress in the channel of MOSFETs on SOI is mandatory for sub-22 nm technological nodes. Its efficiency depends on the device geometry and design. The impact of different steps of the transistor fabrication process (active area patterning, metal gate formation, Source/Drain (S/D) implantation) on the strain in strained Silicon-On-Insulator (sSOI) materials has been measured by Grazing Incidence X-Ray Diffraction (GIXRD). The electrical performance enhancement of MOSFETs on sSOI has also been estimated with respect to SOI (100% mobility enhancement for long and wide nMOS (L=W=10 μm), 35% saturation drive current (IDsat) enhancement for short and narrow nMOS (L=25 nm, W=77 nm)). Innovative strained structures have then been studied. We demonstrate a 37% (18%) IDsat enhancement for pMOS on SOI (sSOI) with SiGe S/D compared to sSOI with Si S/D, for a 60 nm gate length and a 15 nm film thickness. GIXRD measurements, together with mechanical simulations, enabled the study and optimization of new structures using the stress transfer from an embedded and stressed layer (SiGe or nitride) toward the channel.
We developed a heterostructure to assess accurately the strain evolution upon nanopatterning of 15 nm thick tensile strained silicon-on-insulator (SSOI). Here the long-standing concern of substrate background in micro-Raman analysis was circumvented by the introduction of a Ge layer underneath the buried oxide. Unprecedented insights into the strain behavior in SSOI nanostructures were obtained by combining deep UV and visible micro-Raman probes. We found that the formation of edges results in a strong relaxation near the surface parallel to an increase in the strain at the Si/oxide interface. This disparity in the strain evolution between surface and interface leads to the coexistence of compressive and tensile strained regions within the same structure at a lateral dimension of 50 nm. This heterogeneous distribution of strain should be taken into account in the design and fabrication of SSOI-based nanodevices.
