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One of the challenges for bulk-Si FinFET is forming the junction isolation at the 14nm node and beyond. As the fins are scaled, source–drain punch-through can occur, which causes large leakage currents. A punch-through stop (PTS) layer/structure at the bottom of the fin is introduced to suppress this sub-fin leakage current. However, the introducti...
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... is a more attractive n-type dopant because of its high solubility and low diffusion rate compared to antimony (Sb + ) [5,6]. However, the introduction of PTS may result in dopant up-diffusion into the active fin region from the Punch-through stop implant, as shown in Figure 1. This increases the channel doping concentration, resulting in reduced I ON , increased V TH , and eventually increased leakage current due to GIDL, for example. ...
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... 体区穿通是 FinFET 器件结构上的另一个弱点, 来源于栅电极对 Fin 底部控制力的减弱. 为了抑 制体区穿通, 通常采用的办法是进行底部的防穿通注入 [18] , 但是这样引入额外的注入步骤增减了成 本, 高注入剂量也可能破坏 Fin 本征沟道的输运优势和抗涨落优势, 并不是一个理想的方案. 针对该 问题, 人们提出了 Fin 底部局部隔离的办法 [19,20] , 诸如通过 Fin 底部的贯通氧化的办法形成所谓的 Body-on-insulator FinFET 结构 [19] , 如图 5 所示. ...
... However, Si implantation at room temperature has been shown to be not suitable for III-V fin doping in advanced architectures such as finFET or nanowire FETs due to implant induced damage in narrow III-V fins or wires. Hot implant (I/I-HOT) has been developed and shown to eliminate implant damage in the narrow fins of SOI and bulk Si finFETs 84,85 [see Fig. 23]. This is clearly observed in a series of TEM images shown in Fig. 50 that show that I/I-RT forms an amorphous layer around the fin top/sidewalls 159 . ...
... Fig. 23depicts the implant induced damage and proposes to use hot implant as the potential solution84,85 . ...
The economic health of the semiconductor industry requires substantial scaling of chip power, performance, and area with every new technology node that is ramped into manufacturing in two year intervals. With no direct physical link to any particular design dimensions, industry wide the technology node names are chosen to reflect the roughly 70% scaling of linear dimensions necessary to enable the doubling of transistor density predicted by Moore’s law and typically progress as 22nm, 14nm, 10nm, 7nm, 5nm, 3nm etc. At the time of this writing, the most advanced technology node in volume manufacturing is the 14nm node with the 7nm node in advanced development and 5nm in early exploration. The technology challenges to reach thus far have not been trivial. This review addresses the past innovation in response to the device challenges and discusses in-depth the integration challenges associated with the sub-22nm non-planar finFET technologies that are either in advanced technology development or in manufacturing. It discusses the integration challenges in patterning for both the front-end-of-line and back-end-of-line elements in the CMOS transistor. In addition, this article also gives a brief review of integrating an alternate channel material into the finFET technology, as well as next generation device architectures such as nanowire and vertical FETs. Lastly, it also discusses challenges dictated by the need to interconnect the ever-increasing density of transistors.
... Some reports have showed JL bulk FinFET with better sub-threshold swing (S.S.) and DIBL than on a SOI substrate [6]. Unlike SOI with perfect isolated MESA structure, JL bulk FinFETs require punch-through stop (PTS) doping process below the fin channel to suppress junction leakage current [7][8][9]. The additional doping process causes threshold voltage shifts and implant related defects in the bottom of fin, which results in undesirable device variability and degradation. ...
In this paper, one proposed an effective method to enhance current drivability of junctionless FETs (JL-FETs) by utilizing uniaxial tensile strain effects. The strained layers were deposited on JL-FETs on silicon-on-insulator (SOI) and bulk Si wafers, respectively. Strained JL SOI FETs show an extremely low subthreshold swing (S.S.) of 65 mV/decade with ION/IOFF > 10⁹; strained JL bulk FinFETs show an S.S. of 75 mV/decade with ION/IOFF > 10⁷. For strained JL bulk FinFETs, a triangular fin shape could suppress leakage current effectively. Regardless of substrates, JL FETs showed excellent performance owing to uniaxial tensile strain technology. Analysis of leakage current in strained JL FETs included effects on Gate-induced drain leakage trap-assisted tunneling effects were discussed by ID-VG curves under various temperatures and activation energy. Compared with JL SOI gate-all-around structures, JL bulk FinFET possesses higher ID and offer the promise of higher integration flexibility for Si CMOS compatible process for the future applications.
... However, Si implantation at room temperature has been shown to be not suitable for III-V fin doping in advanced architectures such as finFET or nanowire FETs due to implant induced damage in narrow III-V fins or wires. Hot implant (I/I-HOT) has been developed and shown to eliminate implant damage in the narrow fins of SOI and bulk Si finFETs 84,85 [see Fig. 23]. This is clearly observed in a series of TEM images shown in Fig. 50 that show that I/I-RT forms an amorphous layer around the fin top/sidewalls 158 . ...
... Fig. 23depicts the implant induced damage and proposes to use hot implant as the potential solution84,85 . ...
The economic health of the semiconductor industry requires substantial scaling of chip power, performance, and area with every new technology node that is ramped into manufacturing in two year intervals. With no direct physical link to any particular design dimensions, industry wide the technology node names are chosen to reflect the roughly 70% scaling of linear dimensions necessary to enable the doubling of transistor density predicted by Moore’s law and typically progress as 22nm, 14nm, 10nm, 7nm, 5nm, 3nm etc. At the time of this writing, the most advanced technology node in volume manufacturing is the 14nm node with the 7nm node in advanced development and 5nm in early exploration. The technology challenges to reach thus far have not been trivial. This review addresses the past innovation in response to the device challenges and discusses in-depth the integration challenges associated with the sub-22nm non-planar finFET technologies that are either in advanced technology development or in manufacturing. It discusses the integration challenges in patterning for both the front-end-of-line and back-end-of-line elements in the CMOS transistor. In addition, this article also gives a brief review of integrating an alternate channel material into the finFET technology, as well as next generation device architectures such as nanowire and vertical FETs. Lastly, it also discusses challenges dictated by the need to interconnect the ever-increasing density of transistors.
Read More: http://www.worldscientific.com/doi/abs/10.1142/S0129156417400018
Fin field-effect transistor (FinFET) scaling beyond the 10-nm node requires formation of a junction isolation region between the source and the drain to suppress sub-fin leakage current. In this paper, heavy species such as Sb and As were implanted at room temperature to form a punch-through stop (PTS) layer in
${n}$
-Ge substrates. The impact of PTS implants on channel doping and defects, as well as junction leakage, was investigated for bulk Ge
${p}$
-FinFET applications. We report retrograde doping profiles with a low surface (channel) dopant concentration of 4–5
$\times 10^{\textsf {16}}$
cm
<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">−3</sup>
for Sb PTS implants post 550 °C and 650 °C activation anneals. Besides achieving low effective channel doping, the 650 °C high-temperature activation anneal post PTS implant also helps in the reduction of channel defect density. Furthermore, low junction leakage currents are also demonstrated for Sb and As PTS implants with 550 °C and 650 °C activation anneals. To avoid damaging the FinFET channel layer due to PTS ion implantation, Ge homoepitaxy was also studied post Sb PTS implants. However, Sb PTS implants activated at 650 °C without Ge epitaxy exhibit the best results in terms of low channel dopant and defect concentrations, besides junction leakage.
This paper details the application of phosphorus monolayer doping of silicon on insulator substrates. There have been no previous publications dedicated to the topic of MLD on SOI, which allows for the impact of reduced substrate dimensions to be probed. The doping was done through functionalization of the substrates with chemically bound allyldiphenylphosphine dopant molecules. Following functionalization, the samples were capped and annealed to enable the diffusion of dopant atoms into the substrate and their activation. Electrical and material characterisation was carried out to determine the impact of MLD on surface quality and activation results produced by the process. MLD has proven to be highly applicable to SOI substrates producing doping levels in excess of 1 × 10¹⁹ cm⁻³ with minimal impact on surface quality. Hall effect data proved that reducing SOI dimensions from 66 to 13 nm lead to an increase in carrier concentration values due to the reduced volume available to the dopant for diffusion. Dopant trapping was found at both Si–SiO2 interfaces and will be problematic when attempting to reach doping levels achieved by rival techniques.
The influence of carbon on the evolution of boron deactivation was experimentally investigated. The peak profiles of implanted boron overlapped that of carbon in preamorphized silicon. Different annealing conditions were applied to modulate the injection of interstitials from end-of-range (EOR) defects to the recrystallized region. Transient enhanced diffusion was evident during rapid thermal annealing (RTA) at 600°C while significant boron deactivation caused by carbon coimplantation was observed after solid-phase epitaxial regrowth. The degree of boron deactivation is proportional to the implantation doses of carbon and boron, indicating that the pairing of carbon and boron atoms prevents boron activation. However, carbon prevented further deactivation during additional furnace annealing at 750°C after RTA because carbon blocked the reaction between boron and excess interstitials that were generated from the EOR defects.
As dimension of bulk Si field-effect transistors scales down, novel techniques for impurity profile design at channel area are required because suppression of short-channel effects and improvement of on-state current is tradeoff in conventional ion implantation process. In this paper, we demonstrate p-type bulk Si fin field-effect transistors by using solid-source doping for better impurity profile in fin to weaken the tradeoff between suppression of short-channel effects and improvement of on-state current. In this paper, impurity profiles in fin with two different kinds of anneal conditions after fin revelation (1000 °C 30 s and 1050 °C spike) are analyzed, and the better impurity profile at channel area is designed by 1000 °C 30-s anneal for better electrical characteristics. The anneal condition with the better impurity profile in fin shows mobility improvement at long gate length (1 μm) and short gate lengths (60, 70, and 80 nm); subthreshold slope and transconductance are improved at the same time. With those results, we conclude that a fabrication process flow of p-type bulk Si fin field-effect transistors to weaken the tradeoff between suppression of short-channel effects and improvement of on-state current is established with 1000 °C 30-s anneal after fin revelation by using solid-source doping. At the same time, electrical characteristics variation is also suppressed in the case of 1000 °C 30-s anneal.
