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This paper presents an eight-channel time-interleaved (TI) 2.6 GS/s 8-bit successive approximation register (SAR) analog-to-digital converter (ADC) prototype in a 55-nm complementary metal-oxide-semiconductor (CMOS) process. The channel-selection-embedded bootstrap switch is adopted to perform sampling times synchronization using the full-speed mas...
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... ADC prototype was manufactured in a 55-nm one-poly nine-metal (1P9M) CMOS process with a core area of 400 µm × 550 µm, and a large number of decoupling capacitors were filled inside the chip to keep the power supply voltage clean and stable. The die micrograph is shown in Figure 7. The static performance of differential non-linearity (DNL) and integral non-linearity (INL) is shown in Figure 8. ...
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... ADC prototype was manufactured in a 55-nm one-poly nine-metal (1P9M) CMOS process with a core area of 400 μm × 550 μm, and a large number of decoupling capacitors were filled inside the chip to keep the power supply voltage clean and stable. The die micrograph is shown in Figure 7. The static performance of differential non-linearity (DNL) and integral non-linearity (INL) is shown in The output fast Fourier transform (FFT) spectrum is shown in Figure 9 at a 115 MHz input frequency and 2.6 GS/s, with an spurious-free dynamic range (SFDR) of 52.0 dB and signal-to-noiseand-distortion ratio (SNDR) of 41.52 dB. Figure 10 shows SNDR and SFDR versus input frequency at 2.6 GS/s. ...
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The successive approximation register (SAR) analog-to-digital converter (ADC) is currently the most popular type of ADC architecture, owing to its power efficiency. They are also used in multichannel systems, where power efficiency is of high importance because of the large number of simultaneously working channels. However, the SAR ADC architectur...
A 1 GS/s 12-bit pipelined/successive-approximation-register (pipelined/SAR) hybrid analog-to-digital converter (ADC) is presented in this paper, where the five most significant bits are resolved by two cascading 2.5-bit multiplying digital-to-analog converters, and the eight least significant bits are determined by a two-channel time-interleaved su...
This paper presents a foreground digital calibration algorithm based on a dynamic comparator that aims to reduce comparator offset and capacitor mismatch, as well as improve the performance of the successive approximation analog-to-digital converter (SARADC). The dynamic comparator is designed with two preamplifiers and one latch to facilitate high...
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An 11-bit 10 MS/s successive approximation register (SAR) analog-to-digital converter (ADC) is proposed for low-power and small-area applications. A 10-bit differential capacitor–resistor (C–R) digital-to-analog converter (DAC) is used to minimize the area of a DAC. The use of a C–R DAC reduces the capacitor area of a SAR ADC used CDAC by 75%. A ca...
Citations
... Modern electronic communication systems, such as baseband optical communication and satellite communication receivers, have growing demands for high-speed and highresolution analog-to-digital converters (ADCs) [1][2][3][4][5]. A TIADC system composed by several slow but accurate sub-ADCs can meet the requirements of communication systems [6][7][8]. ...
This paper presents a novel digital background calibration technique for timing mismatches in time-interleaved analog-to-digital converters (TIADCs). We reconstruct and eliminate the timing mismatch based on the theory of timing-mismatch-induced spurious signals in the frequency domain. The proposed compensation algorithm utilizes the conjugate property between spurious signals to achieve low complexity. A coarse-fine correction architecture is adopted to eliminate higher-order time-skew errors. A novel feedforward estimation algorithm based on the correlation of adjacent channels is proposed to extract the time-skew errors. Our proposed calibration technique is suitable for an arbitrary number of channels. The simulation results demonstrate that the utilization of the proposed calibration technique yields significant improvements in both the signal-to-noise-and-distortion ratio (SNDR) and spurious-free dynamic range (SFDR). The SNDR and SFDR are improved from 55.82 dB and 56.64 dB to 79.92 dB and 105.98 dB, respectively.
... During the past decade, successive approximation register (SAR) analog-to-digital converters (ADCs) have become a dominant ADC architecture as sub-ADCs of the TI ADC, covering a wide range of resolution and speed owing to advanced process technologies, mostly attributed to their digital friendly architecture [4][5][6][7][8][9][10][11]. The need for high-speed clocks for internal loop operation in a synchronous SAR ADC can be eliminated by using asynchronous architecture [12][13][14]. It could even make the conversion speed faster, because the next comparison can be conducted as soon as the previous decision is completed, without the need to wait for the next clock. ...
This paper presents a high-speed successive approximation register (SAR) analog-to-digital converter (ADC) that takes advantage of both asynchronous SAR ADC and loop-unrolled (LU) SAR ADC. By utilizing the output of the dynamic amplifier (DA) to generate an asynchronous clock, the reset time for the DA can be hidden behind the comparator latching time. Dedicated latches for each digital-to-analog converter (DAC) element eliminate the need for DAC switching logic. The proposed inverter-inserted three-stage comparator significantly reduces the input-referred offset of the comparator. The prototype 6-bit 700 MS/s SAR ADC was implemented in a 28 nm CMOS process and has a small 0.0012 mm2 area. The measured peak DNL and INL without any mismatch calibration were 0.33 and 0.27 LSB, respectively. With Nyquist input, the measured signal-to-noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR) were 34.07 and 47.52 dB, respectively. The power consumption was 1 mW under a supply voltage of 1.0 V, leading to a Walden figure of merit (FoM) of 34.6 fJ/conversion-step at 700 MS/s.
... On the counterpart, this approach substantially limits the possible choices of the sample rate, that, due to additional design constraints, fall upon three values per decade: typically either {2, 5, 10} or {2, 4, 10} [11][12][13]. Consequently, one has poor control of the time interval capture in waveform analysis, and less possibilities for an optimal usage of the memory resources [14,15]. For instance, one can not set coherent sampling conditions in the analysis of steady alternate waveforms, as well as optimal frequency span and resolution in FFT analyses [16][17][18][19]. ...
The time-base used by digital storage oscilloscopes allows limited selections of the sample rate, namely constrained to a few integer submultiples of the maximum sample rate. This limitation offers the advantage of simplifying the data transfer from the analog-to-digital converter to the acquisition memory, and of assuring stability performances, expressed in terms of absolute jitter, that are independent of the chosen sample rate. On the counterpart, it prevents an optimal usage of the memory resources of the oscilloscope and compels to post processing operations in several applications. A time-base that allows selecting the sample rate with very fine frequency resolution, in particular as a rational submultiple of the maximum rate, is proposed. The proposal addresses the oscilloscopes with time-interleaved converters, that require a dedicated and multifaceted approach with respect to architectures where a single monolithic converter is in charge of signal digitization. The proposed time-base allows selecting with fine frequency resolution sample rate values up to 200 GHz and beyond, still assuring jitter performances independent of the sample rate selection.
... References [14,15] are different from the traditional background calibration, the calibration method of the digital-to-analog converter (DAC) in the feedback link is introduced, which further improves the calibration effect. References [16][17][18] analyze the influence of channel mismatch sampling, they use the channel cross feedback mechanism to equalize the mismatch, and design a peripheral delay circuit to compensate for the offset of the calibration clock, which eliminate the energy of harmonics, and improve SINAD; References [19][20][21][22] propose a background calibration method that does not require pre-emphasis based on a 65 nm, 6-bit, 16 GS/s TI ADC. The offset mismatch is reduced after digital calibration, the delay phase locked loop is used to generate 8 sampling interfaces as multi-phase clock generator; References [23][24][25] propose a blind method to estimate channel mismatch and timing skew, this method does not need to know the input signal, as long as it meets the required bandwidth, calibration can be done while ADC is converting, it can be applied to many environments. ...
... According to the accumulative average method, calculate the initial offset mismatch 0,1, … , 1 according to Eq (18), and obtain by taking the difference between and , ...
This article presents a method to calibrate a 16-channel 40 GS/s time-interleaved analog-to-digital converter (TI-ADC) based on channel equalization and Monte Carlo method. First, the channel mismatch is estimated by the Monte Carlo method, and equalize each channel to meet the calibration requirement. This method does not require additional hardware circuits, every channel can be compensated. The calibration structure is simple and the convergence speed is fast, besides, the ADC is worked in background mode, which does not affect the conversion. The prototype, implemented in 28 nm CMOS, reaches a 41 dB SFDR with an input signal of 1.2 GHz and 5 dBm after the proposed background offset and gain mismatch calibration. Compared with previous works, the spurious-free dynamic range (SFDR) and the effective number of bits (ENOB) are better, the estimation accuracy is higher, the error is smaller and the faster speed of convergence improves the efficiency of signal processing.
... In many optical communication infrastructures, in order to meet the broader bandwidth requirements, the sampling frequency and the bandwidth of ADC need to be continuously improved. Researchers have proposed a time-interleaved sampling scheme; the parallel sampling scheme increases the sampling rate to N times that of a single ADC [1][2][3][4][5][6]. ...
In optical communication systems, coherent detection is a standard method. The received signal enters the digital domain after passing through a time-interleaved analog-to-digital converter (TI-ADC). However, the time delay of the ADC brings noise into the signal, which decreases the signal quality; therefore, ADC calibration is essential. At present, there are many calibration methods for time delay, but their performances are not satisfactory at a high sampling frequency. This paper presents a method of time delay estimation and calibration in a coherent optical communication system. First, the expected maximum (EM) method is used to roughly estimate the time delay and then transfer the estimated value into the trained back propagation (BP) neural network to generate more accurate results. Second, the sampled signal is reconstructed, and then a finite impulse response (FIR) filter is designed to compensate for the time delay. There are several advantages of the proposed method compared with previous works: the convergence with a BP network is faster, the estimation accuracy is higher, and the calibration does not affect the sample operation of the ADC working in the background mode. In addition, the proposed calibration method does not need additional circuits and its low power consumption provides more sources for dispersion compensation, error correction, and other subsequent operations in the coherent optical communication system. Based on the quadrature phase shift keying (QPSK) system, the proposed method was implemented in a 16-channel/8-bit, 40-GS/s ADC. After estimation and calibration, the relative error of estimation was below 1%, the signal noise distortion rate (SNDR) reached 55.9 dB, the spurious free dynamic range (SFDR) improved to 61.2 dB, and the effective number of bits (ENOB) was 6.7 bits. The results demonstrate that the proposed method has a better calibration performance than other methods.
... Recently, high-resolution (>10 ENOB (Effective Number of Bits)) and high-speed (>150 MS/s) analog-to-digital converters (ADCs) with low power consumption have become an essential building block in modern wireless communication systems. Owing to the evolution of the CMOS process, the charge-redistribution successive-approximationregister (SAR) ADC is very attractive as a high-performance ADC [1][2][3][4][5]. However, the SAR ADC has a speed bottleneck due to the serial conversion mechanism, and it is difficult to have a high signal-to-noise ratio (SNR) due to the comparator noise. ...
... When the coarse conversion is done, V RES_U is generated based on V ref(i+0. 5) , and V RES_L is generated based on V ref(i−1.5) . Owing to the inter-stage redundancy presented by the proposed over-ranged residue generation technique, a recoverable range is allowed even if comparator noise or amplifier offset occurs, as shown in Figure 8b. ...
This work presents a 12 bit 200 MS/s dual-residue pipelined successive approximation registers (SAR) analog-to-digital converter (ADC) with a single open-loop residue amplifier (RA). By using the inherent characteristics of the SAR conversion scheme, the proposed ADC sequentially generates two residue levels from the single RA, which eliminates the need for inter-stage gain-matching calibration. To convert the sequentially generated the two residues, a capacitive interpolating SAR ADC (I-SAR ADC) is also proposed. The I-SAR ADC is very compact because it consists of the one comparator, a CDAC, and control logic like a conventional SAR ADC. In addition, the I-SAR ADC needs no static power dissipation for the residue interpolation. A prototype ADC fabricated in a 40 nm CMOS technology occupies an active area of 0.026 mm2. At a 200 MS/s sampling-rate with the Nyquist input, the ADC achieves an SNDR (Signal-to-Noise distortion ratio) of 62.1 dB and 67.1 dB SFDR (Spurious-Free Dynamic Range), respectively. The total power consumed is 3.9 mW under a 0.9 V supply. Without any inter-stage mismatch calibration, the ADC achieve Walden Figure-of-Merit (FoM) of 19.0 fJ/conversion-step.
... The temperature estimation function of this type of time domain CMOS temperature sensor is defined as the ratio of two different temperature dependent delay times. The typical structure of this type of temperature sensor, which was proposed by P. Chen et al. in 2010 [38], includes two delay lines, of which delay times vary in a different way from each other with respect to temperature, and a successive approximation register (SAR) control logic [76][77][78][79][80][81][82][83][84][85][86][87] implemented as an FSM. For example, if one of these delay lines is composed of the general inverter type delay cells of Figure 5b, then the other is composed of the delay cells shown in Figure 6b which are less sensitive to temperature [33,38]. ...
Time domain complementary metal-oxide-semiconductor (CMOS) temperature sensors estimate the temperature of a sensory device by measuring the frequency, period and/or delay time instead of the voltage and/or current signals that have been traditionally measured for a long time. In this paper, the time domain CMOS temperature sensors are categorized into twelve types by using the temperature estimation function which is newly defined as the ratio of two measured time domain signals. The categorized time domain CMOS temperature sensors, which have been published in literature, show different characteristics respectively in terms of temperature conversion rate, die area, process variation compensation, temperature error, power supply voltage sensitivity and so on. Based on their characteristics, we can choose the most appropriate one from twelve types to satisfy a given specification.
... Effective number of bits (ENOB), power consumption, and conversion speed along with other parameters measure the performance of ADCs. With complementary metal-oxide-semiconductor (CMOS) technologies entering the submicron domain, the transistor sizing has been downscaled to a few nanometers [5][6][7][8][9]. For low power and medium conversion speed, the SAR type ADC is among the best available choices as in its operation, full conversion is divided into several comparison phases by using only one comparator [10]. ...
This paper presents a wide-range and low phase noise mm-Wave Voltage Controlled Oscillator (VCO) based on the transconductance linearization technique. The proposed technique eliminates the deep triode region of the active part of the VCO, and lowers the noise introduced by the gm-cell. The switch sizes inside the switched capacitor bank of the VCO are optimized to minimize the resistance of the switches while keeping the wide tuning range. A new layout technique shortens the routing of the VCO outputs, and lowers the parasitic inductance and resistance of the VCO routing. The presented method prevents the reduction of the quality factor of the tank due to the long routing. The proposed VCO achieves a discrete frequency tuning range, of 14 GHz to 18 GHz, through a linear coarse and middle switched capacitor array, and offers superior phase noise performance compared to recent state-of-the-art VCO architectures. The design is implemented in a 45 nm CMOS process and occupies a layout area (including output buffers) of 0.14 mm2. The power consumption of the VCO core is 24 mW from the power supply of 0.8 V. The post-layout simulation result shows the VCO achieves the phase noise performances of −87.2 dBc/Hz and −113 dBc/Hz, at 100 kHz and 1 MHz offset frequencies from the carrier frequency of 14 GHz, respectively. In an 18 GHz carrier frequency, the results are −87.4 dBc/Hz and −110 dBc/Hz, accordingly.
... Driven by the rapid development of the information society, the need for systems such as highspeed digital oscilloscopes, optical communications, future mobile communication systems, and direct sampling receivers is growing fast. As the core device, analog to digital converter (ADC) plays an important role in such modern signal processing systems [1][2][3][4][5]. Moreover, the throughput rate of such signal processing systems is often limited by the speed of ADC. ...
This paper presents a 12-bit 2.4 GS/s analog-to-digital converter (ADC) employing four time-interleaved (TI) pipelined channels with a novel on-chip timing mismatch calibration in 40 nm CMOS process. TI architecture can increase the effective sampling rate of ADC but the dynamic performance of TI-ADC system is seriously degraded by offset, gain, and timing mismatches among the channels. Timing mismatch is the most challenging barrier among these mismatches due to the difficulty and complexity of its detection and correction. An automatic wideband timing mismatch detection algorithm is proposed for achieving a wide frequency range of timing mismatch detection without complex calculations. By adopting the proposed mismatch-free variable delay line (VDL), the full-scale traversal timing mismatch correction accomplishes an accurate result without missing codes. Measurement results show that the spurious free dynamic range (SFDR) of the prototype ADC is improved from 55.2 dB to 72.8 dB after calibration at 2.4 GS/s with a 141 MHz input signal. It can achieve an SFDR above 60 dB across the entire first Nyquist band based on the timing mismatch calibration and retiming technology. The prototype ADC chip occupies an area of 3 mm × 3 mm and it consumes 420 mW from a 1.8 V supply.
... Effective number of bits (ENOB), power consumption, and conversion speed along with other parameters measure the performance of ADCs. With complementary metal-oxide-semiconductor (CMOS) technologies entering the submicron domain, the transistor sizing has been downscaled to a few nanometers [5][6][7][8][9]. For low power and medium conversion speed, the SAR type ADC is among the best available choices as in its operation, full conversion is divided into several comparison phases by using only one comparator [10]. ...
This paper presents an energy-efficient low power 10-b 8-MS/s asynchronous successive approximation register (SAR) analog-to-digital (ADC) converter. An inverted common-mode charge recovery technique is proposed to reduce the switching energy and to improve the linearity of the digital-to-analog converter (DAC). The proposed switching technique consumes only 149 CVREF2 switching energy for the 10-bit case. A rail-to-rail dynamic latch comparator is implemented with adaptive power control for better power efficiency. Additionally, to optimize the power consumption and performance of the logic part, a modified asynchronous type SAR control logic with digitally controllable delay cells is adopted. An on-chip reference voltage generator is also designed with an ADC core for practical use. The structure is realized using 55-nm complementary metal–oxide–semiconductor (CMOS) process technology. The proposed architecture achieves an effective number of bits (ENOB) of 9.56 bits and a signal-to-noise and distortion ratio (SNDR) level of 59.3 dB with a sampling rate of 8 MS/s at measurement level. The whole architecture consumes only 572 µW power when a power supply of 1 V is applied.
