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Spintronics is one of the emerging fields for next-generation low power, high endurance, non-volatile, and area efficient memory technology. Spin torque transfer (STT), spin orbit torque (SOT), and electric field assisted switching mechanisms have been used to switch magnetization in various spintronic devices. However, their operation speed is fun...
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... The stochastic process moments are defined by fluctuation-dissipation theory as: where a and b are cartesian components, T is the temperature of the thermal bath to which the spins are coupled. The overall simulation framework showing the incorporation of two temperature model and magnetization switching for circuit applications is shown in Fig. ...
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... Average switching voltage reduction of 32% has been observed with this process. Also, this patterning scheme maintains 10-year data retention and endurance up to 10 8 cycles on 1 kb cells [85] 2022 ...
The need for high-density, higher-speed memory devices has increased tremendously over the last decade. With scaling and integration capacity of traditional memories reaching its limits, new types of memory technologies have come up in the semiconductor market. These new technologies, i.e. non-volatile memories, aim to solve traditional charge-based memory limitations like low dynamic power, higher BW performance, high density and low scaling cost and also aim to solve low-endurance, process issues. Non-volatile memories play an essential role in transforming the semiconductor industry for future use. This paper aims to describe characteristics of different types of non-volatile memories, ‘available’ and ‘emerging’, in the semiconductor industry. Some recent developments are covered as a part of study in the application of all-optical-enabled MTJ, spin-polarized currents, phase conversion and magnetism in the logic and memory domain. In addition, characteristics of different emerging memories such as all-optical switching MTJ, ReRAM, PCM, SOT-MRAM, STT-MRAM, etc. have been discussed on basis of various performance parameters. Non-volatile memories mentioned above not only provides retention period of over 10 years but also ensures endurance over ~ 1010 cycles. The read and write operation latency in these memories is between 1 and 7 ns range which is much better as compared to charge-based memories. The literature comparison analysis along with experimental results summary has been presented in this paper.
With the development of spintronics memory technology, more and more research has been focused on the design of Computing-in-Memory (CiM) architectures using spin devices, including in-memory logic computing and in-memory neural network computing architectures. In this chapter, the focus is mainly on the implementation of in-memory logical/numerical computation using spintronics memory technology and the realization of spintronics neural network architecture. The state-of-the-art designs are reviewed and analyzed, including spin-in-memory logic gates, highly parallel multi-bit spin logic computing architectures, in-memory neural network architectures, and system-level CiM integrated architectures, with an observation of future trends.
Conventional computing architectures based on the von Neumann structure are suffering from the severe ‘memory wall’ issue due to the isolation and speed mismatch between memory and processor. As a promising solution, the concept of logic in-memory (LiM) has been proposed to effectively reduce the overhead of data migration and has been extensively studied in various memory technologies such as SRAM, DRAM, MRAM, ReRAM, etc. Among them, SOT-MRAM combines the advantages of non-volatility, low static power consumption, ultra-fast read/write speed, and high density, has emerged as one of the most promising candidates for low-power LiM implementations. In this paper, four in-memory logic operations, AND, OR, MAJ and full-addition (FA), are proposed based on the Unipolar Switching (US) SOT-MRAM devices. Incorporating the emerging switching behavior of SOT-MRAM, these operations can be performed with the basic memory access operations (read/write) with negligible modifying peripheral circuits. Meanwhile, by optimizing the operation steps, the performance degradation caused by the instability of SOT-MRAM device can be minimized in the proposed LiM architecture. Detailed simulation results show that the proposed design can reduce the latency (energy) of AND, OR operations at least by 71.2%, 74.4% (30.0%, 35.4%) compared with the existing SRAM and STT-MRAM designs. For MAJ and FA operations, the performance is improved by at least 34.7% and 44.8% compared to the existing design. The robustness of our design is demonstrated by the 100% pass of the 1000 samples Monte Carlo simulations for the sufficient switching current margin and the effectiveness of basic operations.
