Data flow in a von Neumann architecture. Simplified representation of the block diagram in [23]. 

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... optical and optoelectronic hardware. The potential of a high optical channel density will only be efficiently exploited if it is supported by an appropriate architecture. Pro- cessor architectures consisting of modules located at central processor buses will only poorly benefit from short-distance optical interconnects. In this case, data that arrive via a 2-D optical interface have to be eventually routed with long on-chip wiring to their final destination on chip. This leads also to an increase of the achievable system clock period. Hence, short-distance optical interconnects in combina- tion with an appropriate architecture offer not only high I/O bandwidth. They avoid long on-chip interconnects too, sup- porting the implementation of systems with low clock period. We show in this paper that fine-grain and massively parallel architectures like neural and reconfigurable computer structures exploit the potential of optical short-distance interconnects much better. In the past, the feasibility of microoptical components for short-distance interconnects has been demonstrated frequently. Besides, a lot of progress was also made by the development of optoelectronic devices and corresponding driver circuits to realize optical transmission and receiving directly on the chip [11], [12]. However, one of the major problems in the future is the integration of optics and electronics. Planar optical integration of free-space optics is an approach to solve this problem resulting in compact and stable systems for optical multichip modules (MCM’s) [13]. In addition, fiber optical interconnects may be used for communication over longer distances ( 10 cm) to connect such MCM’s or packaged OE-VLSI circuits mounted on neighbored printed circuit boards. Such fiber arrays may also be used to perform specific rearrangement operations. In this paper, we present first demonstrator experiments in which a planar optical system is used for the integration of a parallel optical short-distance interconnect scheme to an OE-VLSI circuit. This circuit is based on self-electrooptical effect device (SEED) modulator technology [14]. It was fabricated through the Consortium of Optical and Optoelectronic Technologies in Computing (CO-OP) program at George Mason University sponsored by the Defense Advanced Research Projects Agency [15]. The chip realizes an optoelectronic solution for a binary neural associative memory and a reconfigurable hardware structure. Furthermore, we present results on the fabrication of fiber arrays, which we will use as primary optical part of a future test environment for OE-VLSI circuits before they are integrated in planar optical MCM’s. We are reporting the results of a common interdisciplinary project among optical scientists, electrical engineers, and computer scientists. This paper is structured as follows. In Section II, we describe the architecture model for the binary neural associative memory and explain why we selected this architecture for a realization. We will discuss the background of neural processing in this context and then focus on optoelectronic technology. In Section III, we theoretically derive the throughput performance of the optoelectronic solution and compare it to pure electronic systems. Section IV focuses on the hardware realization. This includes three aspects: design and test of the OE-VLSI chip and the optical interconnects and the integration of both. We conclude our results in Section V. II. A PPROPRIATE VLSI A RCHITECTURES FOR S HORT -D ISTANCE O PTICAL I NTERCONNECTS Due to their inherently irregular architecture, traditional von Neumann structures are not suited to benefit significantly from highly dense optical chip-to-chip interconnections. Architectures that exploit optical interconnections efficiently have to take into account the locality and regularity of optical imaging systems [16]–[18]. Examples for architectures that fulfill these conditions are neural and reconfigurable computing structures [19]–[21]. Although neural architectures are not going to be the mainstream architectures in the future, they exhibit certain features that will be found in more gen- eral-purpose architectures like massively parallel computer systems too. These are large fan-in and fanout, large portion of global interconnects within the chip area, and a parallel memory access. In particular, such interconnect schemes are well suited to be realized by 3-D optical interconnects. This allows one to exploit large chip areas for logic circuitry that are wasted for wiring otherwise. Furthermore, neural structures are well suited for experiments demonstrating the benefits of optoelectronic interconnection topology. First, we explain in this subsection in more detail why the computing performance of traditional von Neumann architectures will not improve by using short-distance optical interconnects. After- wards, we present the architecture model of a binary neural associative memory we selected for implementation with optoelectronic technology. Currently, the architecture setup of most microprocessors resembles strongly the traditional von Neumann principle. Functional units like the control, integer and floating-point unit form a central processing unit (CPU). In the past, the CPU was expanded by more and more memory units like cache and memory management components to diminish the von Neumann bottleneck [22]. But as usual in von Neumann architectures, all functional units are still grouped around a central processor bus. Furthermore, as Fig. 1 shows, a modem microprocessor like the Intel Pentium consists of a variety of modules, like, e.g., the memory management unit, the control unit, and the cache. As illustrated, the number of data bits which are exchanged between those modules on-chip via a central processor bus is varying considerably. The data path width between control and integer unit on one side and the cache on the other side is 320 bits. Whereas the memory management unit and the cache transfer only 96 bits among each other, the floating-point unit needs in a closer distance an internal bus width of 80 bits. This ge- ometrically irregular distribution of on-chip data traffic is in a certain contrast to the regular setup of arrays of mi- crolasers, modulators, or microlenses, which are needed to realize short-distance optical interconnects. As a result, incoming optical input data must be routed with long running wires on an additional metal layer to the final destination on the chip after electrical–optical conversion. A similar situation is given for optical interchip interconnects. In this case, external interconnects located at the circuit’s edge will be replaced by a 2-D array of optoelectronic interconnects, enlarging the number of possible off-chip connections. But again, an irregular data traffic is given because different functional units show different strong data requirements to the chip’s outside world. A more efficient use of short-distance optical interconnects than in von Neumann architectures is guaranteed if the architecture consists of fine-grained, massively parallel architectures [24], [25] with tens to hundreds of thousands of simple processing elements (PE’s) on one chip. Then the high space bandwidth of optical interconnects is exploited best. Furthermore, stacked and optically linked circuit planes [10] allow one to realize 3-D architectures with pipeline processing in superpipelined and superscalar units. The first example of an architecture we selected for a realization with existing OE-VLSI circuit technology is a binary neural associative memory. This architecture was proposed by Palm [26]. It has a series of features that are ideally appropriate for a solution with optical interconnects, as recognized by other groups, too. In [27], a solution for such an architecture based on liquid crystal technology is presented. Our solution uses OE-VLSI circuits and a planar optical system [13] to realize fast operation and compact integration. To un- derstand better the benefits of such an architecture for an optoelectronic solution, we first explain the functionality of the architecture. As usual in an associative memory, we are using a key vector to read out a vector , which was stored before in the associative memory (see Figs. 2 and 3). In addition, in a binary associative memory, all components of the vectors as well as the content of a single associative memory cell have either the value 1 or 0. All memory cells are arranged in a matrix with components . During a learning cycle, the content of is determined as the logical sum of AND opera- tions between the th component of and the th component of for all vector pairs we want to store (1) logical AND (1) logical OR During readout, i.e., in the recognition cycle, a vector matrix product of the input vector with the matrix of associative memory cells is carried out and a subsequent threshold operation is applied to the result to deter- mine the components of the output vector (2). Because the values are all binary, the multiplication is reduced to count logical 1’s along columns in that rows , where the th component of is equal to one. Furthermore, the parallel addressing scheme of such an associative memory can be fully supported using 3-D optical interconnect ...