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A significant portion of the total power consumption in high performance digital circuits in deep sub micron regime is mainly due to leakage power. Leakage is the only source of power consumption in an idle circuit. Therefore it is important to reduce leakage power in portable systems. In this paper two techniques such as transistor stacking and se...
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Citations
... A flip-flop shown in fig 6(a) widely used in all real time applications (TGFF) [16]. To overcome the problem of power consumption two FF designs are proposed. ...
The basic element in sequential circuit design is flip-flop and flip-flops are widely used in memories. This paper outlines the design of Single-Phase Clocking flip-flop using various methods like pass transistor and the transmission gate logic. The main scope of this paper is to design a flip-flop with optimized power. The optimization of power and the reduction in transistor count is achieved by using transmission gates and pass transistor logic. 45nm CMOS based design technology chosen for the implementation technology. The performance metrics of Flip-flop designs were compared with different sequential circuits using transmission gate and pass transistor logic techniques. Pre-layout analysis results indicated that, proposed designs excelled in optimizing the average power. When compared with the other designs, the proposed flip-flop is designed using only 11-transistors and the average power consumption of the proposed flip-flop is bring downed to 108.9 nW. All the designs are simulated and verified with PYXIS tool running on 3.41 GHz processor. These flip-flop designs are best suited for low power and high performance applications.
... Due to this combination, the leakage power is reduced up to a desired level. This functionality explains the low power specification of the design [33]. ...
... Hence, the output voltage oscillates up to -2V DD . In this transition, the sub-threshold leakage is minimized due to the suppression of output voltage [30,33]. ...
This paper represents a low leakage, highly efficient and delay improved 4×1 MUX with MOS based voltage doubler circuit cum augmented sleep transistors MOS configuration with nanoscale structure. The unique newly designed voltage doubler circuit is implemented as an additional circuit at the output of the implemented proposed design to step-up the voltage. It means that the output peak voltage is doubled due to the transient of both positive and negative cycles. This stepped-up voltage may be exploited as a stabilized supply for specific applications. The voltage doubler circuit is not enough to improve the overall performance of proposed 4×1 MUX design. In order to integrate the optimization criterion of leakage power and delay performance, the voltage doubler circuit is utilized along with the MOS configuration of augmented sleep transistors. To minimize the parameter of leakage power dissipation the MOS based voltage doubler circuit cum augmented sleep transistors MOS configuration is introduced. This will mitigate the redundant unused leakage power dissipation of the circuit. This additional circuitry brings out the aspired level of output voltage for the proposed and implemented 4×1 MUX with better performance parameters. The whole simulation has been done for the 45 nm technology. It is finally summarized that the leakage power dissipation is minimized up to 55% just around and the delay performance is also improved up to a desired level due to the utilization of MOS based voltage doubler circuit with the MOS configuration of augmented sleep transistors. In this paper, different combinations of MOS based augmented voltage doubler circuit implemented at the output of 4×1 MUX are represented.
Low power VLSI designs are having wide variety of application usage in real-time. VLSI circuits are analyzed with various power reduction strategies. Existing approaches are used the clock frequency control, switching activity and scaling factor for power reduction. The glitching problem and clock triggering issues are higher therefore; the proposed work utilized the improved circuit of clock gating technique. In this proposed work, the enhanced clock gating with D-latch model is constructed to obtain the less power consumption. The traditional clock gating technique is improved by adding clock triggering on LATCH circuit and adding buffer circuit between the source and load circuitry to reduce the clock switching issues like gitching and clocking activity. Here the SRAM and sequential counter circuits are designed to utilize the power reduction strategy for improving the performance. This is applicable for various applications in real world and utilizing the FPGA and DSP application specific circuits. Experimental results are analyzed to obtain the power reduction result of SRAM and sequential circuit. Area, power, and delay are obtained the better results as compared with the previous work. Overall, design is performed using Xilinx 14.2 ISE suit.
Ensuring correct functionality is the basic objective of any digital design and this can be done only if the circuit obeys all the timing constraints. Static Timing Analysis is the procedure performed to calculate the setup and hold time of any digital circuit and to check for any setup and hold time violations. This paper presents the methodology to perform setup and hold time analysis for different designs of Master Slave D Flip-Flop using 18 nm FinFET technology. FinFET technology was chosen since it is the prevalent technology in the industry. Implementation of D Flip-Flop design, suitable test circuit and timing analysis is performed on the Cadence virtuoso analog design environment tool. Using appropriate excitations, parametric analysis is carried out to obtain the setup and hold time values for various designs of D Flip-Flop including the proposed design. From the results, it was observed that the setup time and hold time varied with different clock edge rates. For the edge rates of 0.01, 0.05, and 0.1 ns, it was observed that the proposed design gave setup times of 54.9, 61.2, and 69.8 ps and hold times of −30.7, −43.6 and, −48.8 ps respectively. On comparing all the results, it was observed that the GDI MUX and pass transistor-based designs gave a good trade-off between transistor count, setup time and hold time. For the proposed design, although the setup times were slightly on the higher side, the hold time values were more negative which is always preferred.
This paper presents a computer program and simulation technique for fast DC analysis of MOSFET based on VLSI circuits. Time-domain analysis of a VLSI-based circuit is determined by a piecewise constant waveform approximation. This approximation is determined by applying the developed DC analysis with initial conditions. The proposed methods like device parameter modeling, circuit-partitioning, and event-driven simulation were implemented and combined with such algorithms as modified nodal analysis (MNA), Katzenelson algorithm, and Gaussian elimination in the form of a circuit simulation program: SAMOC. Time-domain analysis waveforms and benchmark circuit simulation results in comparison of SPICE and SAMOC are presented.
The characteristic and parametric dimensioning of Enclosed Layout (ELT) MOSFET with various geometric sizes and shapes has been taken into consideration for the study of irradiations and leakage at room temperature, which has been confirmed on several technological platforms. Using the most advanced technologies, parametric changes with minimum W/L ratios, layout area and input capacitance to reduce leakage current can improve the performance. The technique of hardening of the MOSFETs in contrary to total-dose radiation effects in space environment built in enclosure to the enclosed transistor for the elimination of edges, responsible of conventional NMOS transistors leakage path creation. High yielding, high level of integration, radiation immune, high speed, low costing and high volume production are the profit advantages of the enclosed layout.
