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This paper considers the applicability of multiple-valued logic
(MVL) circuits in implementation of field-programmable gate arrays
(FPGAs). It proposes an FPGA logic block architecture that features MVL
current-mode CMOS circuitry. The logic block combines the lookup-table
and multiplexer approaches found in commercial FPGAs, and provides
additiona...
Context in source publication
Context 1
... possible basic block is depicted in Figure 5. It comprises the circuit in Figure 3 (which includes four current mode lookup tables), a circuit that converts a 4-valued current signal into two binary voltage signals (given in Figure 2) and flip-flops to facilitate implementation of sequential circuits. ...
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Citations
... The technique of PLA design for MVL has been developed as generalization of well-known PLA based techniques in Boolean algebra [40,41,42]. The development of PLA in Boolean algebra is based on disjunctive normal form dominantly, therefore, the most investigations for PLA design in MVL are implemented in Post's algebra [40,42,43]. At the same time, investigation of PLA design based on Reed-Muller Expression of Boolean function has shown that it has better testability [44,45]. ...
... Different techniques how logic circuits can be realized exist [8,42,43]. One of them is a PLA, which is a combinational logic circuit with a fixed structure that allows realizing any logic function. ...
The binary information technology reaches its limits set by the atomic size miniaturization, by calculation speed and by the fundamental principle of energy dissipation per bit processing. Employing Multiple-Valued Logic (MVL) cells as computing and memory units reduces energy losses and enables to pack unprecedented high-density information, but the current silicon-based material technologies have been studied marginally for the material realization of MVL devices. Here we propose to use the ferroelectrics for the implementation of MVL units using their ability to pin the polarization as a sequence of multi-stable states. More specifically, realization of a Programmable Logic Array (PLA) based on MVL units is considered with application of the ferroelectrics technology in implementation of memory units. The specific of the PLA construction is use of generalized Reed-Muller expression for representation of an MVL function. In this paper, several possible implementations of such PLAs are considered, and their properties are analyzed from logic design point of view.
... MVL is the background of the logic design of multi-valued circuits [1]. Different techniques are used to develop these circuits [8,42,43]. One of these techniques for the design of combinational logic circuits is PLA [42]. ...
... PLA structure is closely correlated with the mathematical background for the representation of logic (Boolean and MVL) functions [9,44]. The technique of PLA design for MVL has been developed as a generalization of well-known PLA based semiconductor techniques for which Boolean algebra is the mathematical background [42][43][44]. In Boolean algebra, disjunctive normal form is typically used for the development of PLA. ...
... In Boolean algebra, disjunctive normal form is typically used for the development of PLA. Its generalization for the realization of MVL functions results into application of Post algebra for PLA design [42][43][44]. There are also studies of PLA design based on Reed-Muller Expression in Boolean algebra [45,46]. ...
Semiconductor devices and binary information technology reach their limits set by the atomic size of miniaturization, calculation speed, and the fundamental principle of energy dissipation per bit processing. Therefore, new technologies in logic design and mathematical approaches must be investigated. Application of multiple-valued logic (MVL) in logic design allows developing gates and circuits with more than two stable states. This enables packing an unprecedented high-density of information. Based on this idea, a new technique of the programmable logic arrays (PLA) construction based on MVL units is considered. The unique aspect of this technique is the application of recurrent generalized Reed–Muller expression (GRME) for MVL function representation. The recurrent procedure for this expression's construction is considered and applied in the PLA development. The proposed structure of PLA consists of two blocks that are memory and logic block. In this paper, we also consider the possibility to use the ferroelectrics for the implementation of cells of the memory block of PLA. The development of gates with multi-stable states is possible by the ferroelectrics ability to pin the polarization as a sequence of stable states.
... The technique of PLA design for MVL has been developed as generalization of well-known PLA based techniques in Boolean algebra [40,41,42]. The development of PLA in Boolean algebra is based on disjunctive normal form dominantly, therefore, the most investigations for PLA design in MVL are implemented in Post's algebra [40,42,43]. At the same time, investigation of PLA design based on Reed-Muller Expression of Boolean function has shown that it has better testability [44,45]. ...
... Different techniques how logic circuits can be realized exist [8,42,43]. One of them is a PLA, which is a combinational logic circuit with a fixed structure that allows realizing any logic function. ...
... There are different techniques for logic circuits design based on MVL elements [27][28][29]. One of these techniques is Programable Logic Arrays (PLA) development that permits to implement any logic function (combinational logic circuits) [28]. ...
Employing many-valued logic (MVL) data processing allows to dramatically increase the performance of computing circuits. Here we propose to employ ferroelectrics for the material implementation of MVL units basing on their ability to pin the polarization as a sequence of multi-stable states. Two conceptual ideas are considered. As the first system, we suggest using the strained ferroelectric films that can host the polarization states, allowing the effective field-induced multilevel switching between them. As the second one, we propose to employ the ferroelectric nano-samples that confine the topologically protected polarization textures, which may be used as MVL structural elements. We demonstrate that these systems are suitable for engineering of the 3-, 4- and even 5-level logic units and consider the circuit design for such elements.
... There are different techniques for logic circuits design based on MVL elements [27][28][29]. One of these techniques is Programmable Logic Arrays (PLA) development that permits to implement any logic function (combinational logic circuits) [28]. ...
Employing many-valued logic (MVL) data processing allows to dramatically increase the performance of computing circuits. Here we propose to employ ferroelectrics for the material implementation of MVL units basing on their ability to pin the polarization as a sequence of multi-stable states. Two conceptual ideas are considered. As the first system, we suggest using the strained ferroelectric films that can host the polarization states, allowing the effective field-induced multilevel switching between them. As the second one, we propose to employ the ferroelectric nano-samples that confine the topologically protected polarization textures, which may be used as MVL structural elements. We demonstrate that these systems are suitable for engineering of the 3-, 4- and even 5-level logic units and consider the circuit design for such elements.
... One of the important advantage of quaternary logic is that has the reduced noise margin when compared to the conventional binary logic. More over if we use the current mode we have to face the problem for the fabrication process and have the high power consumptions [2]. ...
... This function implemented by a quaternary look-up table (QLUT) is defined as g: Qk → Q, over a set of quaternary variables Y=(y0,….. yi ……… yk-1), where the values of a variable yi, as the values of the function g(Y ), can be in Q= {0,1,2,3}. As in the binary case, the number of possible function in QLUTs is given by (2), where b=4. In this case, the number of functions that can be represented is everywhere 4.3×109 for aQLUT with only two quaternary inputs (k=2), which is much larger than for the BLUT [3]. ...
... Due to its reconfigurability, FPGAs play an important role in modern digital systems design, as they allow an earlier time-to-market and reduced engineering change order costs when compared with application-specific integrated circuits (ASICs). An approach to mitigate the impact of interconnections is to use multiple-valued logic (MVL) [3], hence, more information can be carried in each wire, reducing the routing network. Therefore, a single wire carrying a signal with N logic levels can replace log 2 N wires carrying binary signals. ...
... Paulo Flores (S'92-M'02-SM'13) received the Five-Year Engineering, M.Sc., and Ph.D. degrees in electrical and computer engineering from the Instituto Superior Técnico (IST), University of Lisbon, Lisbon, Portugal, in 1989, 1993, and 2001 He has been teaching with IST since 1990, where he is currently an Assistant Professor with the Department of Electrical and Computer Engineering. He has also been with the Instituto de Engenharia de Sistemas e Computadores Research and Development, Lisbon, since 1988, where he is currently a Senior Researcher with the Algorithms for Optimization and Simulation Group. ...
Interconnections are increasingly the dominant contributor to delay, area and energy consumption in CMOS digital circuits. Multiple-valued logic can decrease the average power required for level transitions and reduces the number of required interconnections, hence also reducing the impact of interconnections on overall energy consumption. In this paper, we propose a quaternary lookup table (LUT) structure, designed to replace or complement binary LUTs in field programmable gate arrays. The circuit is compatible with standard CMOS processes, with a single voltage supply and employing only simple voltagemode structures. A clock boosting technique is used to optimize the switches resistance and power consumption. The proposed implementation overcomes several limitations found in previous quaternary implementations published so far, such as the need for special features in the CMOS process or power-hungry current-mode cells. We present a full adder prototype based on the designed LUT, fabricated in a standard 130-nm CMOS technology, able to work at 100 MHz while consuming 122 μW. The experimental results demonstrate the correct quaternary operation and confirm the power efficiency of the proposed design.
... Multiple-valued logic (MVL) has been proposed in the past as a means to reduce the number of wires in a circuit [3]- [5]. In theory, a wire carrying a signal with N logic levels can replace log 2 N wires carrying binary signals. ...
Interconnect has become preponderant in many aspects of circuit design, namely delay, power and area. This effect is particularly true for FPGAs, where interconnect is often the most limiting factor. Quaternary logic offers a means to reduce interconnect since each circuit wire can, in principle, carry the same information as two binary wires. We have proposed in [1] a design implementing a quaternary low-power high-speed look-up table. The main features of this circuit are being based on a voltage-mode structure and using only standard CMOS technology. In this paper we present the design of a prototype implementation and experimental results. These results are discussed and conclusions are drawn that provide further guidelines for improvement.
... By using selective resynchronization approaches, it is possible to also overcome changes to intra-die thermal gradients and hotspots. In future, we will use this network with NoCs [68] and novel FPGA designs [69]. ...
We present a clock distribution network that emphasizes flexibility and layout independence. It suits a variety of applications, clock domain shapes and sizes using a modular, standard cell-based design approach that mitigates the effect of intra-die temperature and process variances. We route the clock line serially, using an averaging technique to eliminate skew between clock regions in a domain. Routing clock lines serially allows optimal wire usage for clock networks by eliminating the redundant wires required to match path delays. Our clock network provides control over regional clock skews, can be used in beneficial skew applications and facilitates silicon-debug. Serial clocking permits the use of routing switches in the clock network and allows post-silicon resizing and reshaping of clock domains. Defective sections of the clock network can be bypassed, providing post silicon repair capability. The system uses a closed-loop synchronization phase to combine the clock skew reduction of an actively synchronized clock network with an open-loop operating phase that minimizes power consumption like passive clock networks. Our clock network provides significant flexibility for application-specific integrated circuit, system-on-chip, and field-programmable gate-array designs, exhibiting good operating characteristics everywhere in the design envelope. Our silicon implementation achieves a maximum edge-to-edge uncertainty of 80 ps for regional clocks, which is roughly equal to the cycle-to-cycle jitter of the on-chip clock source.
... Since designers increasingly replace ASICs with FPGAs, which are not well-suited for floating-point arithmetic even if non-binary [1], there is a renewed interest in fixed-point arithmetic. Allocating bit-widths in a datapath has a direct impact on resources and circuit speed. ...
Range analysis is an important task in obtaining the correct, yet fast and inexpensive arithmetic circuits. The traditional methods, either simulation-based or static, have the disadvantage of low efficiency and coarse bounds, which may lead to unnecessary bits. In this paper, we propose a new method that combines several techniques to perform fixed-point range analysis in a datapath towards obtaining the much tighter ranges efficiently. We show that the range and the bit-width allocation can be obtained with better results relative to the past methods, and in significantly shorter time.
