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Cross section of the fabricated 3.3 kV planar-gate SiC MOSFET. (a) 3D schematic cross section, and (b) top view of planform.
Source publication
Both large current capability and strong short-circuit (SC) ruggedness are necessary for 3.3 kV SiC MOSFETs to improve system efficiency and reduce costs in industrial and traction applications. In this paper, the effects of Junction Field Effect Transistor (JFET) region width and JFET doping (JD) on conduction and SC capability of the 3.3 kV plana...
Context in source publication
Context 1
... on the source and drain, then annealed at 980 ℃ for 2 min by rapid thermal annealing process. A multi-layer metal of titanium (Ti) (20 nm)-Al (4000 nm)-Ti (20 nm) is deposited as a gate metal and is used to interconnect whole cells in the die. The 3D schematic cross-section and top view of the fabricated 3.3 kV planar-gate SiC MOSFET are shown in Fig. 1 (a) and (b), respectively. It consists of a square cell layout with channel length of 1 μm and JFET width (WJFET) of 2.5-4.5 ...
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A new side-contacted field effect diode (S-FED) structure has been introduced as a modified S-FED, which is composed of a diode and planar double gate MOSFET. In this paper, drain current of modified and conventional S-FEDs were investigated in on-state and off-state. For the conventional S-FED, the potential barrier height between the source and t...
Citations
In this work, the influence of JFET region width on device’s performance and avalanche reliability is studied on 1200 V planar-gate silicon carbide (SiC) MOSFETs fabricated on a 4-in SiC wafer. Unclamped inductive switching (UIS) test is conducted to compare the devices under tests (DUTs) avalanche capability at both
${V}_{\text {GS}} ={0}$
V and
${V}_{\text {GS}} = -5$
V. At
${V}_{\text {GS}} ={0}$
V, the best avalanche reliability is achieved with a JFET region width of
${4}~\mu \text{m}$
. Through mix-mode TCAD simulation, channel conduction is found to contribute to the failure at
${V}_{\text {GS}} ={0}$
V. While at
${V}_{\text {GS}} =-5$
V, the best avalanche reliability is achieved with a JFET region width ranging from 2 to
${3}~\mu \text{m}$
. Hole injection is observed in the test and recognized in simulation, which critically influences the DUTs’ avalanche reliability at
${V}_{\text {GS}} = -5$
V.
A review of the short circuit behaviour and short circuit robustness of SiC MOSFETs. For this survey, more than 150 published sources were reviewed with the aim of bringing together all information on the subject that are available so far, but are scattered throughout the literature. Thus, this meta-analysis strives to be a comprehensive overview of the public knowledge on the topic.
