Cross-section HRTEM micrographs of Pt NPs in a NVM capacitor fabricated on a SOI substrate. The HRTEM images were obtained using a mono- chromated and aberration-corrected FEI Titan 80–300 kV S/TEM microscope with a measured spatial resolution of 0.07 nm (in TEM mode). (a) RTA processed NPs. (b) ALD processed NPs. The arrows denote the effective thickness of the oxide layer. The small arrow in Fig. 1(a) denotes the effective thinning of the tunneling SiO 2 due to the embedded Pt NPs. 

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... (MIS) capacitor structures comprising a double layer insulator stack, a thin thermal SiO 2 , and a thick atomic layer deposited (ALD) HfO 2 , fabricated on either bulk silicon or Silicon-on-Insulator (SOI) substrates, serve as a basis for a variety of electronic and optoelectronic devices. A voltage stress process, which causes filamentation in the dielectric and hence introduces a current leakage path, transforms those capacitors into photodetectors and optically controlled varactors which are highly sensitive over a broad spectral range. 1,2 The photo-detectors, so obtained, exhibit low dark currents and high responsivities in the wavelength range from 245 nm to 880 nm, 1,2 and the optically controlled varactors offer very large capacitance tuning ratios for moderate illumination intensities. 2 The addition of semiconductor or metal nano particles (NPs) placed between the two dielectric layers changes the capacitors into nonvolatile memory (NVM) cells with very large memory windows, where the NPs serve as effective charge storage nodes 3–8 with the hysteresis being controllable by illumination. 8,9 This paper described detailed studies of MIS devices that contain Pt NPs fabricated using a low temperature ALD process. Pt was chosen as the NP material due to its large work function difference with silicon that ensures well con- fined electrons and holes. 3,4,10 The large ratio between the potential well depth and the Coulomb charging energy increases the density of trapped charges per particle. 4,8 The most common process to form metal NPs starts with the evaporation of a thin metal film which undergoes high temperature (600 C–800 C for Pt) rapid thermal annealing (RTA). 4–6 Annealing initiates dewetting 4 which results in an ensemble of small particles having average diameters of 4–5 nm which are fully separated from each other. Using this process in conjunction with SOI substrates introduces a problem stemming from the poor thermal properties due to the thick SiO 2 box layer separating the device layer from the bulk silicon. Under the high temperature process, contaminants migrate to the interfaces between NPs and both insulator layers, which causes an enhancement of the charge/discharge processes due to local states outside the NPs. 8 Additionally, the Pt NPs may react with the SiO 2 sub- layer resulting in Pt silicide 11 which thins, in turn, the effective tunneling layer. Above and beyond that, the Pt NPs can actually migrate into the SiO 2 layer further shrinking the tunneling layer. 8 This is clearly seen in Fig. 1(a), which shows a high resolution cross section transmission electron microscope (HRTEM) image of RTA processed Pt NPs, embedded between SiO 2 and HfO 2 layers processed on a SOI substrate. An alternative process to form Pt NPs is to fabricate them in-situ with the HfO 2 layer by ALD. The low temperature (300 C) ALD process ensures that the NPs do not migrate into the SiO 2 layer and the in-situ process avoids contamination stemming from moving the sample between processing systems. A cross section HRTEM micrograph, Fig. 1(b), clearly shows the Pt NPs placed on top of a 2.9 nm thick SiO 2 tunneling layer. A plan-view image of the NPs obtained from a high resolution scanning electron microscope (HRSEM) is shown in Fig. 2(a). Fig. 2(b) describes a histogram of the NP size distribution measured for approximately 900 particles. More than 60% of NPs’ diameter of these ALD processed Pt NPs is 4–5 nm, approximately the same as the sizes of typical NPs fabricated by RTA. The low temperature technique to form Pt nanoparticles was reported in Refs. 12 and 13 and was used effectively for improved catalysts and catalytic fuel cells. 14,15 A non-volatile memory MIS structure fabricated on a bulk silicon substrate that used ALD Pt NPs embedded between a 6 nm thick thermal SiO 2 tunneling layer and an HfO 2 blocking layer which was annealed at 450 C for 5 min was reported in Ref. 16. The thick tunneling layer ensured good retention properties, and the entire process lends itself to standard CMOS processing. However, no previous work addressed the use of a SOI substrate in conjunction with ALD processed NPs. SOI substrates have significant advan- tages due to their widened spectral response 1,2,17,18 and the low temperature process adds a major improvement as clearly seen in Fig. 1. We describe first a systematic study of NVM MIS capacitors with embedded Pt NPs fabricated by ALD. The capacitors were characterized in the dark and under illumination. These capacitors were also voltage stressed, turning them into optically sensitive varactors and photo detectors. The nonlinear behavior of the current-voltage and capacitance-voltage characteristics of these voltage stressed devices was studied. The dependence on illumination intensity and measurement frequency of single devices as well as back to back connected pairs of diodes (which exhibit bipolar hysteresis characteristics) was measured. The key role played by the Pt NPs was clearly identified. Planar MIS structures were fabricated on a SOI substrate comprising a 2.9 l m thick phosphorous doped n-Si layer with a resistivity of 90 X cm, grown on top of a 1.3 l m thick SiO 2 spacer. The thickness of the silicon device layer was chosen based on Ref. 17. Spectroscopic ellipsometry was employed to measure the wavelength dependent extinction coefficient k k of a Si device layer covered with a 2.9 nm thermal SiO 2 tunneling film. From k ð k Þ , it is straightforward to calculate the absorption coefficient and light penetration depth which are shown in Fig. 3(a) as red and blue traces, respectively. Such a SOI substrate avails a measurable photo sensitivity in the range of 245 nm to at least 880 nm. The 2.9 nm thickness of the thermal SiO 2 tunneling layer was shown in Refs. 1 and 2 to be optimal when followed by a 20 nm ALD HfO 2 blocking layer. It enables a controllable filamentation process of the dielectric stack at moderate stress voltages and yields low dark currents in the photodetectors. Nevertheless, the 2.9 nm tunneling layer is thinner than the commonly used value of more than 3.4 nm, which is needed to enact a Fowler- Nordheim tunneling process, 19 and hence, the retention properties of the present device are somewhat inferior. A $ 3 nm thick Pt film was deposited on top of the thermal SiO 2 layer by ALD using (Trimethyl)methylcy- clopentadienylPlatinum (IV) (MeCpPtMe 3 ) in an oxygen environment and at a substrate temperature of about 300 C. The thin Pt film cannot maintain a homogeneous form and breaks up into an ensemble of individual particles which are separated from each other as shown in Fig. 2(a). These Pt NPs were subsequently covered by a 20 nm thick HfO 2 blocking layer deposited in-situ by the ALD system. Spectroscopic ellipsometry measurements were also used to extract the absorption coefficient and penetration depth spectra of the entire structure (Si device layer, SiO 2 tunneling layer, and the HfO 2 blocking layer) with and without the Pt NPs. The enhancement of the absorption coefficient due to the Pt NPs is moderate but is clearly seen in the wavelength range of 400–500 nm. The enhancement is highlighted in the two insets which are zoom images of the 350–500 nm wavelength range. The reason behind the improvement was not fully clarified. A plasmonic enhancement was ruled out due to the small size of the NPs. A possible reason is a slight change in the effective refractive index of the dielectric stack and a consequent enhanced transmission through it which practically enhances the absorption. Similar base structures but with a tunneling oxide thickness of 3.2 nm and 3.6 nm were fabricated simultaneously on a boron doped bulk p-silicon substrate. Diodes were con- structed by depositing Ti/Pd/Pt/Au stacks for both gate and back contact electrodes in the SOI based structures, while, for the devices based on bulk substrates, Ti/Pd/Pt/Au electrodes comprised the gate contacts and Al was used for the back contact electrodes. The filamentation paths in the dielectric stack were obtained by voltage stressing the capacitors using several ms long pulses with an amplitude of slightly below 12 V, which is close to, but lower than, the voltage causing hard breakdown. A schematic cross section of the device is shown in Fig. 4. The optical input port is the area between the center gate contact (whose area is 7.85 Â 10 À 5 cm 2 ) and the ring back contact. The area of the optical window was 1.225 Â 10 À 4 cm 2 . The experimental set-up is described schematically in Fig. 4(b). Current-voltage (I-V) characteristics were measured using an Agilent 4155C Semiconductor parameter analyzer. Capacitance-voltage (C-V) characteristics were obtained from an HP4192A LF impedance analyzer; for single devices, it was operated in the parallel mode, while for two back to back connected diodes, we employed the series impedance mode. The optical characterization used a light emitting diode (LED) array which avails collimated illumination in the 265–880 nm wavelength range. The LED output was coupled to the diode under test via a lensed fiber or a large curvature lens. The corresponding illumination spot areas for the fiber and lens were 8.1 Â 10 À 6 cm 2 and 4.9 Â 10 À 2 cm 2 , respectively. Measured C-V characteristics of an unstressed ...