Convex warpage on the surface of a 140-mm silicon wafer by vapor deposition of Si 3 N 4 with 

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... f being the biaxial film stress, S and f the Young’s modul i of carrier substrate and foil, respectively, ν S being P oisson’s ratio, t S and t f the substrate and film thickness, respectively, and R the radius of curvature of silicon substrate after polymer layer deposition. We assumed that the 6-inch silicon wafer was perfectly flat prior to processing. Table 1 lists the material parameters used in this study. Since wafer bow is conveniently measured by using a profilometer, we need to convert the results from both simulations and measurements to either curvature or wafer bow. Figure 4 shows the comparison of analytical calculation based on Stoney’s formula to measurements. As shown in Figure 4, the measured wafer bow is higher than the calculated one. This divergence is attributed to an overestimation of the thickness of BCB and polyimide, as those films are typically reduced in volume after bring cured, which limits the exact stress calculation based on as-deposited thickness. Not only, BCB and polyimide cause tensile stress on the surface of the carrier; also the thin layer of metal in the last step can cause plastic deformation and intensify the tensile stress. To address this problem, the deposition of a film deposited either on the frontside, causing excess compressive stress, or a film on the backside, causing tensile stress, can be used. Treatment from backside is not suitable due to possible contaminations afterwards with processing tools. Although, surface etching or heating can reduce the amount of pressure on the surface of the carrier, the best way is to use a thin layer on the carrier surface which generates compressive stress on the silicon carrier substrate and, thus, provides the required stress and warpage offsets. PECVD SiO 2 and Si 3 N 4 are good candidates for this purpose, because both materials have a CTE that is smaller than that of silicon. Therefore, they can be used to produce a compressive stress on the surface of bare silicon before any device processing step. Generated stress due to chemical vapor deposition (CVD) of Si 3 N 4 and SiO 2 depends on many factors same as SiH 4 pressure flow, ratio of SiH 4 to NH 3 in the process chamber, process temperature and pressure. After several experiments with different thicknesses and recipes for SiO 2 and Si 3 N 4 , we opted for CVD of Si 3 N 4 with a film thickness of 1.5μm and a SiH 4 pressure flow of 150 sccm. Reducing the pressure flow of SiH 4 in case of similar NH 3 flow, can change the substrate conductivity which should be taken into account, depending on the particular device processing and application. Figure 5 shows the generated convex bow of the bare silicon wafer by vapor deposition of Si 3 N 4 with same deposition recipe and different thicknesses. In this comparison, 1.5 μm Si N generates approximately 50 μm higher bow than 1 μm Si 3 N 4 . Based on our requirement for compensating around 150 μm concave warpage, 1.5 μm Si 3 N 4 was the better choice. With considering this kind of warpage compensation, the process condition for embedding TM ChipFilm dies in polymers is shown in Table 2. With compressive stress induced by Si 3 N 4 deposition, in each process step, the amount of stress on surface is equal to the sum of the stresses from each layer. The initial convex bow of 117 μm on carrier is reduced to below 90 μm after coating BCB, as illustrated in Figure 6.a. Based on this figure, the primary convex warpage due to deposition of Si 3 N 4 on the silicon wafer will be reduced by thermo-mechanical induced stress of each coated polymer layer on the silicon carrier and in the key point step of using processing tool which is AlSiCu metallization and structuring, wafer is in approximately flat state. In the last step, after releasing the fabricated device in foil, carrier will return to the initial state (convex warpage). Therefore, the silicon carrier can conveniently be reused as a process carrier, which makes the proposed fabrication process cost efficient. In comparison with Figure 6.a, warpage history plot of the substrate carrier without stressor layer during device fabrication is shown in Figure 6.b. As is illustrated in Figure 6.b, approximately 120 μm concave warpage in AlSiCu metallization step, makes any handling and further process impossible. The results in this paper show that process- induced warpage of the substrate carrier can effectively be reduced to allow for CMOS- compatible fabrication of foil-based devices on that carrier. Deposition of a 1.5-μm stressor layer prior to foil-based device processing is instrumental in providing a stress and, thus, warpage offset to effectively lower the average degree of warpage. After releasing the foil-based device, the carrier with remaining stressor layer returns to the initial warpage level, thus allowing to reuse the carrier substrate for consecutive processing. The authors would like to thank the members of the IMS process line for sample preparation. The German BMBF is acknowledged for financial support within the project KoSiF (Project ID. ...