Fig 2 - uploaded by Jens Verbeeck
Content may be subject to copyright.
Source publication
This paper presents the DC behavior of transistors with finger layout and with gate enclosed layout in a 0.18m CMOS technology under the influence of gamma-radiation. The threshold voltage shift and the drain current mismatch before and after irradiation has been investigated up to a total ionizing dose of 100kGy.
Context in source publication
Context 1
... with the same ratio as transistor T1 but with different width and length. 4 transistors (T2, T4, T5 and T6) have an equal area but different width en length. In this experiment we were only limited to test one matching structure due to the physical constraints of the irradiation procedure. The configuration of the transistor array is shown in Fig. 2. The transistors in the same column have shared drains. Transistors in the same row have a common gate. They all have shared sources and ...
Similar publications
In this work, a design of ultra-compact plasmonic modulator is proposed and numerically analyzed. The device layout utilizes alternative plasmonic materials such as transparent conducting oxides and titanium nitride which potentially can be applied for CMOS compatible process. The modulation is obtained by varying the carrier concentration of the t...
Layout strategies including source edge to substrate space (SESS) and inserted substrate-pick stripes of gate-grounded NMOS(ggNMOS) are optimized in this work for on-chip electrostatic discharge (ESD) protection. In order to fully investigate influences of substrate resistors on triggering and conduction behaviors of ggNMOS, various devices are des...
This paper presents a D/A converter with a 14-bit intrinsic linearity in 0.5µm CMOS technology, which has been designed using a systematic design methodology for current-steering D/A converters. A flexible architecture is proposed for which the design parameters are calculated using a performance-driven top-down design methodology. The layout of th...
Citations
... The matching of the input pair mainly determines the opamp offset, which reflects a shift in the DAC transfer curve. The radiation-induced threshold voltage shift does not influence the transistor threshold voltage mismatch, as assessed in [29]. We applied a variant of the common centroid topology of an ELT MOS to achieve the physical matching of the input stage. ...
This work presents a rad-hard 12-bit 3 MS/s resistor string DAC for space applications. The converter has been developed using rad-hardened techniques both at architecture and layout levels starting from a conventional topology. The design considers the different effects of the radiation that could damage the circuits in space environments. The DAC has been developed and integrated a standard CMOS 0.13 μm technology by IHP, using RHBD techniques. Low Earth Orbit (LEO) requires a TID value of around 100 krad (Si), according to the expected length of the mission. The temperature range is between −55 °C and 125 °C. The DAC power budget is similar to that of terrestrial applications. The measured INL (Integral Non-Linearity) and DNL (Differential Non-Linearity) are better than 0.2 LSB, while the ENOB (Effective Number Of Bits) at a 3 MS/s clock exceeds 9.7 bits while loading a 10 pF capacitor. The DAC has been characterized under radiation, showing a fluctuation in the analog output lower than 2 LSB (mainly due to measurement uncertainty) up to 500 krad (Si). Power consumption shows a negligible increase, too. A 10-bit version of the same DAC as the downscaled 12-bit one has been developed as well.
... An important class of effect in MOS transistors is the Total Ionizing Dose (TID), which causes electrical degradation due to the accumulation of trapped charges in the insulation oxides, affecting the threshold voltage ( V th ) of transistors, the leakage current and the carrier mobility, among other parameters [30][31][32]. These effects usually depend on biasing, switching frequencies, and size of the transistors [3,14,21,34,37] and may even lead to complete system failure. ...
This paper describes the main failure mechanism of charge redistribution Successive Approximation Register (SAR) Analog-to-Digital Converters (ADCs) under radiation. Results of two different radiation experiments (gamma and X-ray) each considering two identical 130nm, 8-bit SAR ADCs, operating with distinct sampling rates, showed that lower sampling frequencies cause the converters to fail at lower accumulated dose, while increasing the sampling frequency increases the converters robustness to radiation. A SPICE model of a SAR ADC is used to simulate radiation induced leakage effects, considering the same technology node and operating conditions of the tested converters. A very good agreement between simulation results and gamma irradiation experimental data allows us to explain the main failure mechanism, which is related to leakage in switches connected to the programmable capacitor array of the internal DAC of the converter.
... During irradiation it is clear from Figure 13 that the DNL bounds are expanding with increasing dose. This was as expected since the mismatch between CMOS devices increased with dose [25]. The limit of the DNL error that indicates if the TDC is still performing sufficiently, is ±1 LSB. ...
This article presents a radiation tolerant single-shot time-to-digital converter (TDC) with a resolution of 15.6 ps, fabricated in a 65 nm complementary metal oxide semiconductor (CMOS) technology. The TDC is based on a multipath pseudo differential ring oscillator with reduced phase delay, without the need for calibration or interpolation. The ring oscillator is placed inside a Phase Locked Loop (PLL) to compensate for Process, Voltage and Temperature (PVT) variations- and variations due to ionizing radiation. Measurements to evaluate the performance of the TDC in terms of the total ionizing dose (TID) were done. Two different samples were irradiated up to a dose of 2.2 MGy SiO 2 while still maintaining a resolution of 15.6 ps. The TDC has a differential non-linearity (DNL) and integral non-linearity (INL) of 0.22 LSB rms and 0.34 LSB rms respectively.
... The reason for the failure starting at the LSBs may be explained, because the LSB switches are usually composed of smaller transistors, in order to save silicon area, since they have to charge and discharge smaller capacitances. For this reason, TID effects may be more severe at the transistors of such switches due to their reduced dimensions (W/L) [27]- [29]. Additionally, a leakage-induced charge error in smaller capacitors of the array has a higher relative impact than for the higher capacitors. ...
This paper describes the results of a total ionizing dose test on a data acquisition system (DAS) protected with a design diversity redundancy technique. The DAS is composed of three analog-to-digital converters (ADCs) and two voters, implementing different levels of diversity (architectural and temporal). This system is implemented on a 130-nm commercial mixed-signal (MS) programmable system-on-chip (PSoC 5) from Cypress Semiconductor. The system was tested under
<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">60</sup>
Co gamma radiation with a dose rate of 1 krad(Si)/h reaching a total dose of 242 krad(Si). One of the system copies presented a significant degradation on its linearity during the irradiation, while the others kept the functionality with less severe degradation, evidencing the advantage of using diversity to improve resilience in MS redundant systems. Additionally, dynamic parameters of the ADCs are evaluated, and failure mechanisms are discussed.
... The reason for the failure starting at the LSBs may be explained, because the LSB switches are usually composed of smaller transistors, in order to save silicon area, since they have to charge and discharge smaller capacitances. For this reason, TID effects may be more severe at the transistors of such switches due to their reduced dimensions (W/L) [27]- [29]. Additionally, a leakage-induced charge error in smaller capacitors of the array has a higher relative impact than for the higher capacitors. ...
In this work a data acquisition system, based on a design diversity redundant scheme, is tested under total ionizing dose effects. The data acquisition system is composed by three ADCs and two voters, implementing different levels of diversity (architectural and temporal). This system is implemented on a 130nm commercial mixed-signal programmable SoC (PSoC 5), from Cypress Semiconductor. The system was tested under 60 Co gamma radiation with a dose rate of 1 krad(Si)/h reaching a total dose of 242 krad(Si). One of the system copies presented a significant degradation on its linearity during the irradiation, while the others kept the functionality with less severe degradation, evidencing the advantage of using diversity to improve resilience in mixed-signal redundant systems.
... For instance, 1% V TH mismatch in some critical transistors had greater impact on performances than a 10% V TH variation uniformly on all transistors. Since radiation has impact on mismatch of transistors [16], it is important to identify the most sensitive transistors for mismatch at each performance. Thus the V TH of NMOS and PMOS were shifted individually for + 5% and − 5%, respectively, while all other Table 1 Op-amp specifications. ...
... In [16] the radiation effects upon the mismatch of identically laid out transistor pairs is presented, and the results indicate that the mismatch becomes smaller with increasing overdrive voltage gradually moving the transistors operating region from weak to strong inversion mode. ...
This work presents a rail-to-rail operational amplifier hardened by design against ionizing radiation at circuit level, using only standard layout techniques. Not changing transistor layout, for instance by using enclosed layout structures, allows design and simulation using the standard models provided by the foundry. The circuit was fabricated on a standard 0.35 μm CMOS process, and submitted to a total ionizing dose (TID) test campaign using a ⁶⁰Co radiation source, at a dose rate of 0.5 rad(Si)/s, reaching a final accumulated dose of 500 krad(Si). The circuit proved to be radiation tolerant for the tested accumulated dose. The design practices used to mitigate TID effects are presented and discussed in detail.
... In [9,10] experimental radiation data regarding the output offset and open loop gain of bipolar and CMOS commercial Operational Amplifiers (OpAmps) were presented. Considerations on the impact of transistors sizing on the TID effects and radiation-hardening-by-design approaches using ELT (Enclosed Layout Transistor) are discussed in [11,12]. ...
... Regarding Radiation Hardened-By-Designed (RHBD) techniques, a popular layout technique applied to digital circuits to cope with TID is the Enclosed Layout Transistor (ELT) [11,12]. However, design of analog circuits with this technique is not a very simple task, since it does not allow arbitrary W/L ratios required in analog designs. ...
Analog integrated circuits operating in radiation environments. In previous irradiation experiments performed on a switched-capacitor filter, implemented in a programmable analog array, it was observed a sudden recovery of the device performance during the irradiation, while increasing the accumulated dose. In some cases the considered performance parameters (such as the total harmonic distortion) may even be enhanced if compared to the pre-irradiation measurements, in specific accumulated dose intervals. This behavior is associated to partial inactivity windows in the internal components of the device. Spice simulations considering two complementary architectures of a simple CMOS Operational Amplifier (OpAmp) are performed, aiming to understand the origins of this effect. Results indicate that shifts on the operating point of the amplifier building blocks are responsible for the degradation and recovery of the OpAmp performance. Results also show that specific architectures, as well as, application constraints (such as the external feedback and the input signal amplitude and frequency) may result in different robustness levels related to the linear applications of the OpAmps in radiation environments.
Performance degradation of standard time-to-digital converters (TDCs) is inevitable due to the effects of ionizing radiation. In this article, the tradeoffs of different mitigation techniques for TDC architectures are presented. As the effect of radiation is challenging for such high-performance circuits in the state-of-the-art technologies, architectures that can compensate for radiation effects have become a necessity for TDCs to operate in these harsh radiation environments. By looking into the functionality of different architectures focusing on improving radiation tolerance, the main weak and strong points of different TDC architectures, including the compensation circuitry, are described. Possible solutions to those weak points are presented.
We present the design, fabrication, and radiation testing of a custom 20-channel application-specific integrated circuit (ASIC) for amplification and digitization of microvolt signal levels from space instrumentation (e.g., thermopile sensors) operating in harsh space radiation environments. The ASIC is fabricated in a commercial 180-nm complementary metal oxide silicon (CMOS) process node using a combination of radiation hard by design and discrete-time analog signal processing to mitigate leakage, offset, 1/
$f$
, and thermal noise. The chip has an input-referred integrated noise voltage of 190 nV in a 240-Hz bandwidth. Irradiation with very high total ionizing dose (TID) and high-energy heavy ions was carried out to evaluate the chip’s radiation hardness. The chip’s postradiation performance evidenced parametric immunity to greater than 50 Mrad (Si) TID and no single-event latch-up up to at least 123.6 MeV-cm
<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>
/mg linear energy transfer.
