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9 — Complex multiplication datapath: (a) 20-bit Multiply Instruction, (b) Possible inputs to complex multipliers, (c) 33 to 16-bit converter
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Rapidly evolving wireless standards use modern techniques such as turbo codes, Bit Interleaved coded Modulation (BICM), high order QAM constellation, Signal Space Diversity (SSD), Multi-Input Multi-Output (MIMO) Spatial Multiplexing (SM) and Space Time Codes (STC) with different parameters for reliable high rate data transmissions. Adoption of such...
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Citations
... The module shown in Fig. 2 called NISC_CCASM can perform complex addition, subtraction, negation and conjugation. It has similar architecture as the combined complex adder, subtractor and multiplier (CCASM) [3]. Complex number inversion is obtained by using resources in NISC_CCASM in addition to a pre-computed lookup table (LUT) to retrieve the inverse of a 2 +b 2 as shown in (11). ...
... Regarding the inverse of 3×3 matrices, we use the same approach as in [3] by converting the 3×3 matrix to a 4×4 matrix and then applying the same formula derived above for 4×4 matrix inversion. The proposed conversion is done by copying all three rows of 3×3 matrix into first three rows of 4×4 matrix and then putting zeros in all elements of fourth row and fourth column except in their intersection where 1 should be placed. ...
... Table 1 summarizes the synthesis results whereas Table 2 shows the number of clock cycles required for the computation of the equalization coefficients and the estimated symbols. The results are in addition compared with that of EquASIP, which is an ASIP with a custom instruction set dedicated for MMSE-IC equalization [3]. Both processors support same flexibility parameters and use identical computational resources. ...
The variety of wireless communication standards and their corresponding applications requires more and more flexible, yet efficient, implementations. The emerging flexibility need induces a new challenge when added to the ever increasing requirements in terms of high throughput and low complexity. This paper presents a design of an application-specific processor dedicated for a minimum mean square error interference cancellation (MMSE-IC) linear equalizer (LE) used in iterative multi-input multi-output (MIMO) turbo receiver. The explored design approach applies static scheduling of datapath control signals. The proposed architecture supports the requirements of flexibility for different MIMO system configurations concerning channel time selectivity and transmission diversity. In order to evaluate the efficiency of the adopted architecture model for this kind of applications and requirements, a fair comparison is conducted with a state-of-the-art application specific instruction-set processor (ASIP) implementation. The obtained results illustrate a significant performance improvement in terms of execution time and implementation area while using identical computational resources and supporting same flexibility parameters.
... NISC_CCASM shown in Fig.4 is a NISC module that has similar architecture as the combined complex adder, subtractor and multiplier (CCASM) [8]. It can perform all complex addition, subtraction, negation and conjugation. ...
... Using 16-bit signed representation with different bits for integer and fractional part in different computation steps ensures low performance loss for all supported configurations and enables the reuse of hardware resources. The needed precision for each arithmetic, load or store operation was achieved via long simulations [8].All used adders and subtractors are capable to detect overflow/underflow occurrence and to fix the output at its maximum/minimum values. Fixed point converter module was established to perform the conversion at the output of each multiplier. ...
... Table 1 shows the number of clock cycles required for the computation of the coefficients using our proposed design. The results are in addition compared with that of EquASIP, which is an ASIP with a custom instruction set dedicated for MMSE-IC equalization [8]. Both processors use identical computational resources and support same flexibility parameters. ...
Many application-specific processor design approaches are being proposed and investigated nowadays. All of them aim to cope with the emerging flexibility requirement combined with the best performance efficiency. Application Specific Instruction-set Processor (ASIP) design approach is among the most explored, and thus in many application domains. However, this concept implies a dynamic scheduling of a set of instructions which generally lead to an overhead related to instruction decoding. To reduce this overhead, other approaches were proposed using static scheduling of datapath control signals. In this paper, we explore this last approach and illustrate its benefits through a design case-study on MMSE MIMO equalization. The proposed design has common main architectural choices as a state-of-the-art ASIP for comparison purpose. The obtained results illustrate a significant improvement in execution time while using identical computational resources and supporting same flexibility parameters.
