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Complete 16-Bit Asynchronous Adder Block Diagram. 

Complete 16-Bit Asynchronous Adder Block Diagram. 

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Figure 1: Complete Block Diagram of a 4-bit MCC adder. 
Table 1 : Comparison of 32bit Asynchronous Adders.
Figure 2: 4-Bit MCC Block. 
Figure 3: Block Diagram of Synchronous 16-Bit Adder. 
+7 Figure 4: Layout of the 16-Bit MCC Dynamic Adder. 
Comparison of an Asynchronous Manchester Carry Chain Adder to a Synchronous Manchester Carry Chain Adder
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We compare two 16 bit adders based on the Manchester Carry Chain (MCC) circuit topology using the TSMC .25 μm process technology. The first circuit is a synchronous 16 bit adder based on an optimized 4-bit MCC where the carry out of each of the 4-bit MCCs are ripple carried into the next MCC block through an edge sensitive D-Flip Flop. The second c...
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... four clock cycles or delay the inputs by the number of clock cycles it takes for a valid carry- out signal to appear. We chose to delay the data by one cycle (Z ) for A<4:7>, B<4:7>, two clock cycles (Z ) for A<8:11>, B<8:11>, and three clock cycles (Z ) for A<12:15>, B<12:15>. The sum bits are delayed in a similar fashion to make sure the data arrive on the same clock cycle. The circuit is designed to operate at a clock frequency of 500 MHz and has a latency of four clock cycles. The area of the synchronous adder is 320x210 m , as shown in Figure 4, and the number of transistors uses was 884. This circuit took approximately 160 man-hours to design and verify using a professional grade EDA tool using the nominal TSMC25 corner model provided by NCSU [10], and MOSIS [11]. The majority of the time was spent designing and verifying the adder. B. Asynchronous Adder Our Asynchronous dynamic 16-bit adder, as shown in Figure 5, is divided into four stages. Each stage pipelines the carry out by using Muller –C elements. Each adder is a modified 4-bit MCC adder (Figure 6), where the clock signal is replaced with the appropriate Request signal. The Request signal performs the pre-charge and evaluate function, and is delayed by two inverter propagation delays before being fed into the GKP and Sum block. This ensures that the data are monotonic. Then registers are used to hold the data until the calculation is complete. The Muller-C elements were implemented in static CMOS (Figure 7), and the Done blocks were implemented in footed dynamic logic with no weak keepers (Figure ...