Table 1 - uploaded by Shi-Yu Huang
Content may be subject to copyright.
Source publication
This paper presents a low-power SRAM design with quiet-bitline architecture by incorporating two major techniques. Firstly, we use a one-side driving scheme for the write operation to prevent the excessive full-swing charging on the bitlines. Secondly, we use a precharge-free pulling scheme for the read operation so as to keep all bitlines at low v...
Context in source publication
Context 1
... comparison, we also implemented a conventional SRAM macro with the same configuration using the common low-power architecture with two-stage NAND-decoder, the wordline pulse control and low-power sensor amplifiers. Table 1 Access Time: The time required to complete a read or write operation. It can be seen that the new quiet-bitline architecture consumes only 1.5mA supply current on the average, i.e., 15.6% of the baseline architecture, or only 5.9% of the one produced by a memory compiler. ...
Similar publications
In this work, a radiation hardened low-voltage memory cell for ultra-low power operation is proposed. The proposed 13T bitcell is implemented in a standard 0.18μm CMOS process and is shown to tolerate upsets with charge deposits as high as 500 fC through a dual-driven internal self-correction mechanism.
Gain-Cell embedded DRAM (GC-eDRAM) has recently been recognized as a possible alternative to traditional SRAM. While GC-eDRAM inherently provides high-density, low-leakage, low-voltage, and 2-ported operation, its limited retention time requires periodic, power-hungry refresh cycles. This drawback is further enhanced at scaled technologies, where i...
Citations
... Because of the banked register file organization, a doubling in capacity means a doubling in the number of entries of each bank, which means a doubling in bitline length. Since most of the dynamic power consumed in an SRAM is due to bitline charging [5], a doubling in bitline length also doubles the consumed dynamic power per register read. ...
GPUs rely on large register files to unlock thread-level parallelism for high throughput. Unfortunately, large register files are power hungry, making it important to seek for new approaches to improve their utilization. This paper introduces a new register file organization for efficient register-packing of narrow integer and floating-point operands designed to leverage on advances in static analysis. We show that the hardware/software co-designed register file organization yields a performance improvement of up to 79%, and 18.6%, on average, at a modest output-quality degradation.
... The dynamic power involving the switching of signals is consumed in operations such as wordline decoding, bitline charging and discharging, sense amplification, etc. The static power is consumed when there is a direct path from VDD to ground during memory access [1]. As technology advances, more devices are integrated in a system and therefore, a chip consumes more power. ...
... The immediate advantage is that all charging/discharging power associated with the bit lines can be eliminated [11]. Shin-Pao and Cheng Shi-Yu Huang [1] presents a low-power SRAM design with quiet-bitline architecture by incorporating two major techniques. Firstly, a one-side driving scheme for the write operation to prevent the excessive full-swing charging on the bitlines. ...
... Both the write and read operations is modified and the immediate reward is that all charging/discharging power associated with the bitlines can be eliminated dramatically. To achieve this goal, both the write and read operations need to be modified [1]. ...
... The steady state power consumption of the cell is controlled by subthreshold leakage currents, so a larger threshold voltage is often used in memory circuits. To reduce area, the cell layout is highly optimized to eliminate all wasted area [5]. ...
Today VLSI circuit fabrication technology has reached in nanometer dimension. When CMOS technology superseded BJT technology, very low leakage current was one of the main advantages for CMOS circuits. But in nm range, as threshold voltage, channel length, and gate oxide thickness are reduced, leakage current issue is becoming one of the major problems. On the other side, due to huge use of portable devices, low power circuit is in high demand. In this paper simulation results of single cell SRAM are shown. Three different techniques are tested by 90 nm technology file on Cadence platform. Leakage current has significantly reduced from nA range to pA range after applying the techniques. Index Terms—Leakage, 90 nm, DRG Cache, Drowsy cache, Stacking effect, SRAM.
... In recent years as the need of leakage reduction in high-processors and microcontroller architectures, memory structures increases, there have been many research activities on low-voltage SRAM dynamic and standby techniques. Most of the researchers reported circuit techniques in this area focusing on the designs at the sleep mode, .g., an array of dynamically-controlled sleep transistors was used to provide a finely programmable standby V DD [2]. ...
... If the value of the stored bit in the target cell is opposite to the value being written, then cell flipping process will take place. At the end of write operation all bit-lines pre-charged to the VDD and get ready for next read or write operation [2]. ...
The emerging Wireless Sensor Network technologies are facilitating novel applications in health monitoring, industrial monitoring and security surveillance. The small physical dimensions of wireless sensor nodes often restrict the energy source to a small battery. The limited energy consumption requirement demands for ultra-low power sensing, processing and communication. This paper targets the modeling and simulation of CMOS leakage currents and its minimization approach to reduce the power consumption by a single cell SRAM cache. The popular approaches for leakage reduction are the data retention gated ground, and dynamic threshold voltage for cache. The work focuses on the simulation of a SRAM Cell for the data retention gated ground and drowsy mode SRAM Cell which shows that the current reduction of around 25% in s simulation model, respectively in comparison with the conventional cell with no current reduction technique.
... If the value of the stored bit in the target cell is opposite to the value being written, then cell flipping process will take place. At the end of write operation all bit-lines pre-charged to the VDD and get ready for next read or write operation [2]. ...
... The sense amplifier is turned on to amplify the small difference voltage at bit-line pair into full-swing logic signals.At the end of read operation all bit-line precharged to the VDD [2]. In this paper we have a brief discuss about different type of leakage current present in MOS transistors. ...
The growing demand in the multimedia rich applications are motivating the low-power and high-speed circuit designer to work more closely towards the design issues arising from the design trade-offs in power and speed. This paper targets the modeling and simulation of CMOS leakage currents and its minimization approach to reduce the power consumption by a single cell SRAM cache. The popular approaches for leakage reduction are the data retention gated ground, a drowsy mode, and dynamic threshold voltage for cache. The work focuses on the simulation of a SRAM Cell for the data retention gated ground and drowsy mode SRAM Cell which shows that the current reduction of around 20% in first and 25% in second simulation model, respectively in comparison with the conventional cell with no current reduction technique.
... Conventionally, bitline (BL) power and wordline (WL) power are two main factors of SRAM active power. BL power can be reduced by decreasing its capacitance or voltage swing, such as references [1], [2], and [3]. Besides, WL power can also be reduced by shortening the WL length. ...
Low power SRAM plays a key important role on SoC designs. In this paper, low-power floating bitline Read/Write scheme and Write assistant circuits are proposed. Read/Write replica circuits are also designed for wide-voltage range operations. A 32-Kb SRAM subarray is implemented in UMC 90 nm CMOS technology. It can operate at 1 GHz when Vdd is 1 V and at 143 MHz when Vdd is 0.5 V. Moreover, it consumes around 6.6 mW to 670 uW during access cycles.
... However, their performance is bit-width dependent: They have reported to achieve 90% of write power savings under 256 bit-widths however their reduction ratio decreases when bit-width becomes smaller. In [7], Cheng et al. devised a single bit-line driving technique for the write operation in SRAM to eliminate the excessive full charging on the bit-line pair. They force a strong '0' signal in a single side of bit-lines while leaving the other side of bit-lines to be float. ...
This paper presents a power reduction mechanism for the write operation in register files (RegFiles), which adds a conditional charge-sharing structure to the pair of complementary bit-lines in each column of the RegFile. Because the read and write ports for the RegFile are separately implemented, it is possible to avoid pre-charging the bit-line pair for consecutive writes. More precisely, when writing same values to some cells in the same column of the RegFile, it is possible to eliminate energy consumption due to precharging of the bit-line pair. At the same time, when writing opposite values to some cells in the same column of the RegFile, it is possible to reduce energy consumed in charging the bit-line pair thanks to charge-sharing. Motivated by these observations, we modify the bit-line structure of the write ports in the RegFile such that i) we remove per-cycle bitline pre-charging and ii) we employ conditional data dependent charge-sharing. Experimental results on a set of SPEC2000INT / MediaBench benchmarks show an average of 61.5% energy savings with 5.1% area overhead and 16.2% increase in write access delay.
... Static RAM cells are used in a wide variety of applications. These range from memory arrays to ICs of all kinds containing embedded SRAMs [1,2,4]. As the demand for reduced power and delay in components containing SRAMs increases, adjustments will need to be made to meet these requirements. ...
... There have been many proposed designs for SRAM cells that increase performance in some way, but the six-transistor (6T) differential memory cell is still recognized as being a good balance between size and performance [3,5,6]. There have also been proposals for different methods of accessing memory cells that improve on speed and/or power [3,4,5,7]. One such method, as is described in [4], focuses on reducing the voltage level on the bit-lines during read and write operations in order to minimize power consumption. ...
... There have also been proposals for different methods of accessing memory cells that improve on speed and/or power [3,4,5,7]. One such method, as is described in [4], focuses on reducing the voltage level on the bit-lines during read and write operations in order to minimize power consumption. The problem with this design is that while it significantly reduces power, it also causes delay to increase. ...
A novel design for decreasing energy and delay during the read cycle of a standard six-transistor differential SRAM cell is presented in this paper. Removal of the pre- charge transistors from the bit-lines of the SRAM reduces energy consumption. This also eliminates the need for a pre- charge phase which decreases the total delay of a read cycle. Additional logic to improve the speed of a read and to ensure that the bit-lines retain a sufficient voltage difference is placed just before the output on the bit-lines. This is especially significant in the design of pipelined memories where the delay per stage is determined by the time it takes to read a value from a cell as opposed to decoding an address or generating the output of the SRAM. Circuit simulations in 180-nm CMOS show a decline in energy consumption by a minimum of 9.2% and up to 98.6%. Worst case delay is reduced by 27.6%. The following paper explains the proposed read logic in detail, describes the techniques used for the analysis, and compares the results with the standard method for fast, low-power read accesses.
... Static random access memories (SRAMs) are used extensively in all kinds of systems and are found in almost every integrated circuit as an embedded component. They are known for their large storage density and small access latency [2,7]. This section discusses the features of the SRAM block and the different metrics used to analyze and compare different SRAM implementations. ...
... A half-swing bit-line design and quiet bit-line architecture, which keeps the bit-lines near GND at all times, have also been created [3,7]. Divided word-line approaches have been taken as well to reduce the large line capacitance [3]. ...
... Divided word-line approaches have been taken as well to reduce the large line capacitance [3]. Other designs implement charge sharing, recycling, or recovering to reduce power [2,7]. The problem with many of these solutions is that by reducing power significantly, they tend to increase the delay of a memory access. ...
Thesis (M.S. in computer engineering)--Washington State University, August 2006. PDF file. System requirements: Adobe Acrobat Reader. Includes bibliographical references (p. 83-84).
