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7: Comparison of power, area and energy consumption for 8-bit and 16-bit micro-tasks.  

7: Comparison of power, area and energy consumption for 8-bit and 16-bit micro-tasks.  

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Wireless Sensor Networks (WSN) is a new and challenging research field for embedded system design automation. Engineering a WSN node platform is a tough challenge, as the design must enforce many severe constraints among which energy consumption is often the most critical one due to the small size of a node and its difficult access after deployment...

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A wireless sensor network (WSN) node may need to process signals from various sensors and perform different transceiver tasks apart from being able to change its functions dynamically. A controller in the node is therefore required to execute different control tasks to manage its resources implying that flexibility is a key concern. Microcontrollers and FPGAs have been proposed to address the need for flexibility at the cost of reduced energy efficiency. In this thesis, ultra-low power flexible controllers for WSN nodes based on reconfigurable microtasks are explored. A reconfigurable microtask is a digital control unit with a reconfigurable finite state machine (FSM) and datapath. Scalable architectures for reconfigurable FSMs along with variable precision adders in datapath are proposed for flexible controllers in this work. Power gating is considered for FSMs and adders for low power operation. First, the design issues in power gating are studied extensively. Models for estimation of key design parameters of power-gated circuits are derived at gate level. Next, power gating opportunities are determined in reconfigurable adders and FSMs proposed for microtasks. In adders, reconfigurability is used for varying the precision of operation and saving energy by power-gating unused logic. Power gating at the level of lookup table logic is proposed to achieve active leakage power reduction in reconfigurable FSMs. The proposed models are then applied to analyze energy savings in logic clusters due to power gating. Power estimation results show good performance of proposed architectures with respect to different metrics relative to others in the design space of controllers.