Figure - available from: Advanced Intelligent Systems
This content is subject to copyright. Terms and conditions apply.
Source publication
The sustainability of ever more sophisticated artificial intelligence relies on the continual development of highly energy‐efficient and compact computing hardware that mimics the biological neural networks. Recently, the neural firing properties have been widely explored in various spiking neuron devices, which could emerge as the fundamental buil...
Similar publications
This paper describes in detail the implementation of a finite element technique for solving the compressible Navier-Stokes equations that is provably robust and demonstrates excellent performance on modern computer hardware. The method is second-order accurate in time and space. Robustness here means that the method is proved to be invariant domain...
Citations
... W HEN studying compute-in-memory (CIM) architectures [1], [2], [3], monolithic 3-D (M3D) integration techniques can provide significant advantages in terms of latency, area, and power consumption [4]. In M3D CIM architectures, nonvolatile memory (NVM) arrays are fabricated in the back-end-of-line (BEOL), while the peripheral circuitry resides in the front-end-of-line (FEOL). ...
This article presents a comprehensive physics-based model for back-end-of-line (BEOL)-compa-tible oxide–semiconductor-based ferroelectric field-effect transistors (FeFETs). The proposed model describes the polarization switching behavior and enables bidirectional bias sweeps for the hysteretic
$\textit{I}_{\textit{D}}\textit{V}_{\textit{G}}$
curve. The model has been validated against a TCAD model as well as experimental results. Simulations using the proposed model show that polarization switching during the erase operation is primarily influenced by the fringing field in the absence of holes in the amorphous channel. Furthermore, the memory window (MW) increases as the channel length decreases, which is attributed to the enhanced influence of the fringing field in shorter channel devices, resulting in a larger portion of negative polarization being switched during the erase operation. Simulations using this model suggest an MW of 1.2 V, which shows excellent agreement with experimental data.
... However, in these spiking neurons, which operate the integration step without a capacitor, external reset circuits are essential for periodic IF operation and an I-V convertor using OP-AMP is also required to receive the current signal from the synaptic device array. In terms of entire spiking neuron circuit, the energy consumption can be significantly increased due to the operation of external circuits that require additional voltage supply 30 . FBFET and FeFET neurons can emulate neuronal behavior without peripheral circuitry but they need a large number of the components (typically 10 and 8) including two capacitors and have high power consumption (≤ 18.8 pJ/spike and ≤ 369 pJ/spike) 18,29 . ...
We demonstrate a highly biomimetic spiking neuron capable of fast and energy-efficient neuronal oscillation dynamics. Our simple neuron circuit is constructed using silicon–germanium heterojunction based bipolar transistors (HBTs) with nanowire structure. The HBT has a hysteresis window with steep switching characteristics and high current margin in the low voltage range, which enables a high spiking frequency (~ 245 kHz) with low energy consumption (≤ 1.37 pJ/spike). Also, gated structure achieves a stable balance in the activity of the neural system by incorporating both excitatory and inhibitory signal. Furthermore, inhibition of multiple strengths can be realized by adjusting the integration time according to the amplitude of the inhibitory signal. In addition, the spiking frequency can be tuned by mutually controlling the hysteresis window in the HBTs. These results ensure the sparse activity and homeostasis of neural networks.
... Recent directions in neuromorphic spiking circuit is to reduce the use of capacitor or fully eliminate them 99 . However, systems made on memcapacitive technology could be at least 8 × more energetically efficient that with resistive devices 31 while other theoretical work suggest that memcapacitive reservoir computing could be efficient computationally efficient 91 . ...
There is an increasing need to implement neuromorphic systems that are both energetically and computationally efficient. There is also great interest in using electric elements with memory, memelements, that can implement complex neuronal functions intrinsically. A feature not widely incorporated in neuromorphic systems is history-dependent action potential time adaptation which is widely seen in real cells. Previous theoretical work shows that power-law history dependent spike time adaptation, seen in several brain areas and species, can be modeled with fractional order differential equations. Here, we show that fractional order spiking neurons can be implemented using super-capacitors. The super-capacitors have fractional order derivative and memcapacitive properties. We implemented two circuits, a leaky integrate and fire and a Hodgkin–Huxley. Both circuits show power-law spiking time adaptation and optimal coding properties. The spiking dynamics reproduced previously published computer simulations. However, the fractional order Hodgkin–Huxley circuit showed novel dynamics consistent with criticality. We compared the responses of this circuit to recordings from neurons in the weakly-electric fish that have previously been shown to perform fractional order differentiation of their sensory input. The criticality seen in the circuit was confirmed in spontaneous recordings in the live fish. Furthermore, the circuit also predicted long-lasting stimulation that was also corroborated experimentally. Our work shows that fractional order memcapacitors provide intrinsic memory dependence that could allow implementation of computationally efficient neuromorphic devices. Memcapacitors are static elements that consume less energy than the most widely studied memristors, thus allowing the realization of energetically efficient neuromorphic devices.
... A well-known problem in such configured passive RRAM arrays is the sneak current [25,26]. Whereas there are ongoing studies to enhance the intrinsic properties of the RRAM devices to mitigate the sneak current problem, the most straightforward approach is to connect the RRAM synapses to the ground of neuron circuits using various amplifiers [27][28][29]. However, various challenges in the integration of passive RRAM arrays with analog neuron circuits still remain to be addressed. ...
In asynchronous Spiking Neural Networks (SNNs), the voltage division between passive resistive random-access memory (RRAM) arrays and neuron circuits presents a significant challenge, affecting the overall network accuracy and power efficiency. This study introduces the quantized-weight-splitting method (QWSM) as a novel solution to address this challenge. The QWSM optimizes and splits the quantized weights using the static read distortion owing to voltage division. The QWSM successfully guarantees inference accuracy and reduces power consumption. To validate the QWSM, the fabricated RRAM devices were measured, and a fitting model was carefully developed to describe their behavior, showing a strong correlation with measured data. In SNN simulations using the fitting model, the inference accuracy was improved across various weight quantization levels when the QWSM was applied. Moreover, the QWSM led to a substantial reduction in the average power consumption. Specifically, Compared to a network configured to have the smallest combined conductance of RRAMs for low-power operation, the network applying the QWSM showed a 12.56 -% reduction in average power per synapse. This power-saving feature, combined with improved accuracy, positions the QWSM as a valuable tool for efficient SNN design using passive RRAM arrays. Our findings highlight the potential of the QWSM in advancing neuromorphic computing with better energy efficiency and accuracy robustness.
... (32)(33)(34). The zeroes of the trace of the matrix indicate the points where the eigenvalues become purely imaginary, = 0 , Eq. (28). These are the points of the Hopf bifurcation, marked in red in Fig. 29c. ...
Neurons, which are made of biological tissue, exhibit cognitive properties that can be replicated in various material substrates. To create brain-inspired computational artificial systems, we can construct microscopic electronic neurons that mimic natural systems. In this paper, we discuss the essential material and device properties needed for a spiking neuron, which can be characterized using impedance spectroscopy and small perturbation equivalent circuit elements. We find that the minimal neuron system requires a capacitor, a chemical inductor, and a negative resistance. These components can be integrated naturally in the physical response of the device, instead of built from separate circuit elements. We identify the structural conditions for smooth oscillations that depend on certain dynamics of a conducting system with internal state variables. These state variables can be of diverse physical nature, such as properties of fluids, electronic solids, or ionic organic materials, implying that functional neurons can be built in various ways. We highlight the importance of detecting the Hopf bifurcation, a critical point in achieving spiking behavior, through spectral features of the impedance. To this end, we provide a systematic method of analysis in terms of the critical characteristic frequencies that can be obtained from impedance methods. Thus, we propose a methodology to quantify the physical and material properties of devices to produce the dynamic properties of neurons necessary for specific sensory-cognitive tasks. By replicating the essential properties of biological neurons in electronic systems, it may be possible to create brain-inspired computational systems with enhanced capabilities in information processing, pattern recognition, and learning. Additionally, understanding the physical and material properties of neurons can contribute to our knowledge of how biological neurons function and interact in complex neural networks. Overall, this paper presents a novel approach toward building brain-inspired artificial systems and provides insight into the important material and device considerations for achieving spiking behavior in electronic neurons.
... To avoid detrimental voltage fluctuations due to signal interferences, operational amplifiers (op-amps) are introduced between neural components. Specifically, a voltage follower [i.e., isolator 1 (Iso1)] is placed between the N1 and the synapse (38), and an inverting amplifier plus a Howland current pump (39,40) for voltage-to-current conversion (i.e., Iso2) are installed between the synapse and the N2 (41). The synaptic weight (w) here is defined as the absolute value of the inverting amplifier's gain (i.e., the ratio of the resistance across the op-amp over the effective synapse resistance) ( fig. ...
The cointegration of artificial neuronal and synaptic devices with homotypic materials and structures can greatly simplify the fabrication of neuromorphic hardware. We demonstrate experimental realization of vanadium dioxide (VO2) artificial neurons and synapses on the same substrate through selective area carrier doping. By locally configuring pairs of catalytic and inert electrodes that enable nanoscale control over carrier density, volatility or nonvolatility can be appropriately assigned to each two-terminal Mott memory device per lithographic design, and both neuron- and synapse-like devices are successfully integrated on a single chip. Feedforward excitation and inhibition neural motifs are demonstrated at hardware level, followed by simulation of network-level handwritten digit and fashion product recognition tasks with experimental characteristics. Spatially selective electron doping opens up previously unidentified avenues for integration of emerging correlated semiconductors in electronic device technologies.
... However, the conventional complementary metal-oxide semiconductor-(CMOS-)based neuron circuit occupies large chip areas because it requires a large number of transistors and capacitors for generating spike signals. In contrast, the neuron circuit area can be 10 times smaller by using novel devices, such as magnetoresistance memory (MRAM) Liang et al., 2020), phase-change memory (PCM) (Tuma et al., 2016), and threshold switching (TS) selector (Park et al., 2016;Song et al., 2018;Grisafe et al., 2019;Hatem et al., 2019;Hua et al., 2019), which is beneficial for ultrahigh density neuromorphic computing applications (Liang et al., 2021). ...
... Among several novel device-based neurons, thresholdswitching selector-based neurons (TS neurons) are especially promising for ultra-high density neuromorphic architectures due to their simpler and smaller neuronal circuits (Liang et al., 2021). A circuit-level model solving Kirchhoff 's Law based on the resistor-capacitor (RC) equivalent circuit has been proposed to describe the behavior of TS neurons (RC Model) (Chen et al., 2016;Wang et al., 2020). ...
... Therefore, the TS selector with larger τ 0 and A may require an additional external integration capacitor to maintain a reasonable V th , which on the other hand increases the circuit footprint and t on and decreases the spike frequency. The energy consumption per spike of the neuron circuit could also increase due to slow spiking (Liang et al., 2021). Table 1 lists the reported parameters of τ 0 and A of different TS devices (Park et al., 2016;Yoo et al., 2017;Lee et al., 2019bLee et al., , 2020, and the simulated t on and V th of the neuron circuit based on the V-t Model are indicated in Figure 8. ...
In this study, we constructed a voltage–time transformation model (V–t Model) to predict and simulate the spiking behavior of threshold-switching selector-based neurons (TS neurons). The V–t Model combines the physical nucleation theory and the resistor–capacitor (RC) equivalent circuit and successfully depicts the history-dependent threshold voltage of TS selectors, which has not yet been modeled in TS neurons. Moreover, based on our model, we analyzed the currently reported TS devices, including ovonic threshold switching (OTS), insulator-metal transition, and silver- (Ag-) based selectors, and compared the behaviors of the predicted neurons. The results suggest that the OTS neuron is the most promising and potentially achieves the highest spike frequency of GHz and the lowest operating voltage and area overhead. The proposed V–t Model provides an engineering pathway toward the future development of TS neurons for neuromorphic computing applications.
Current advancements in neuromorphic computing systems are focused on decreasing power consumption and enriching computational functions. Correspondingly, state-of-the-art system-on-chip developers are encouraged to design nanoscale devices with minimum power dissipation and high-speed operation. This paper deals with designing a sense amplifier based on side-contacted field-effect diodes to reduce the power-delay product (PDP) and the noise susceptibility, as critical factors in neuron circuits. Our findings reveal that both static and dynamic power consumption of the S-FED-based sense amplifier, equal to 1.86 μW and 1.92 fW/GHz, are × 243.03 and × 332.83 lower than those of the conventional CMOS counterpart, respectively. While the sense-amplifier circuit based on CMOS technology undergoes an output voltage deviation of 170.97 mV, the proposed S-FED-based one enjoys a minor output deviation of 27.31 mV. Meanwhile, the superior HIGH-level and LOW-level noise margins of the S-FED-based sense amplifier to the CMOS counterparts (∆NMH = 70 mV and ∆NML = 120 mV), respectively, can ensure the system-level operation stability of the former one. Subsequent to the attainment of an area-efficient, low-power, and high-speed S-FED-based sense amplifier (PDP = 187.75 × 10–18 W s) as a fundamental building block, devising an innovative integrate-and-fire neuron circuit based on S-FED paves the way to realize a new generation of neuromorphic architectures. To shed light on this context, an S-FED-based integrate-and-fire neuron circuit is designed and analyzed utilizing a sense amplifier and feedback loop to enhance spiking voltage and subsequent noise immunity in addition to an about fourfold increase in firing frequency compared to CMOS-based ones.
Synaptic devices store the synaptic weight in spiking neural networks (SNNs). However, because synaptic devices are based on memory cells, their synaptic weights are vulnerable to temperature variations, which significantly degrade network accuracy. To implement temperature-robust asynchronous SNNs, neurons with captive synaptic devices (CSD neurons) are proposed in this study. Captive synaptic devices that mimic the temperature characteristics of synaptic devices are located parallel to the integration capacitors. By using the captive synaptic devices for the membrane potential reset, the CSD neurons are inherently equipped to counteract temperature-induced variations. The validity of the CSD neurons was experimentally confirmed using two types of synaptic devices: poly Si-channel charge-trap flash synaptic devices and resistive random access memory devices. When applied to the street view house numbers (SVHN) dataset, the SNNs with CSD neurons successfully maintained a constant inference accuracy value (95.00 %) from 300 to 360 K, even if the output current of the synaptic devices doubled.
Spiking neural networks (SNNs) employ discrete spikes that mimic the firing of neurons in biological systems to process and transmit information. This characteristic enables SNNs to effectively capture temporal dynamics and capitalize on the time information inherent in time‐varying inputs, such as motion, audio/video streams, and other sequential data. Currently, most hardware implementations of SNNs are designed to use rate‐coding, where information is encoded in the rate of spikes. However, it still remains challenging for the hardware implementation of temporal coding in SNNs, which allows for higher input sparsity and exploits additional dimensions such as precise spike timing and relative spike timings. This study presents hardware implementations of SNNs constructed by organic electrochemical transistors (OECTs), processing temporal‐coded information. The protic dynamics in response to electrical stimuli enable the emulation of temporal integration, reset, and leaking of membrane potential in a simple leaky integrate‐and‐fire (LIF) neuron circuit. By utilizing these features, the emulated LIF neuron can be employed to construct SNNs capable of processing temporal‐coded information in complex tasks including coincidence detection and dynamic handwriting recognition, exhibiting high performance and good tolerance even when dealing with noisy datasets.
