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(Color online) Schematic cross-section of a-Si:H TFT used in this work.
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We report the intrinsic and extrinsic electrical characteristics of advanced multilayer amorphous silicon (a-Si:H) thin-film transistor (TFT) with dual amorphous silicon nitride (a-SiN X :H) and a-Si:H layers. The thickness effect of the high electronic quality a-Si:H film on the transistor's electrical property was investigated; with increasing fi...
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Citations
... and K of 0.7 V, 1.32, and 11.9 cm 2 V Àc s À1 , respectively. The second method (Method 2) first extracts V T from the maximum of @l inc /@V GS (i.e. the second derivative of I D vs. V GS ) [15,17]. We assume that @l inc /@V GS increases in the subthreshold region and decreases in the threshold region due to the difference properties of deep gap and band tail states in a-ITZO films [18]. ...
... fluorine-based gas and hydrazine monohydrate) on the TFT electrical characteristics, and concluded that dry etching degrades the field-effect mobility of the a-Si:H TFT [12]. With our best effort, however, we cannot find a published study that assesses the influence of a wide array of back channel etchants, with distinct etching chemistries and mechanisms, on the electrical performance of the advanced a-Si:H TFT's [23]. The advanced a-Si:H TFT is a transistor with a multi-layer structure in the gate dielectric and channel region. ...
... c o m / l o c a t e / m e e two-step plasma enhanced chemical vapor deposition (PECVD). This structure was designed to maximize both device performance and manufacturing production throughput [23]. In this study, we compare the impact of different BCE etchants on the characteristics of the inverted staggered advanced a-Si:H TFT, and identify a promising dry etchant that is capable of producing transistors with comparable electrical performance as the device etched by a wet etchant. ...
... All the transistors have the same channel widths (121 lm) and channel lengths (103 lm). Afterward 3500 Å A 0 of high deposition rate a- SiN X :H (G2), 500 Å of low deposition rate a-SiN X :H (G1), 1400 Å A 0 of high deposition rate a-Si:H (A2), 300 Å of low deposition rate a-Si:H (A1), and 700 Å A 0 of n + a-Si:H (phosphorous doped to 1%) are sequentially deposited using PECVD to form the dual-layer gate insulator, dual-layer active channel layer, and the source/drain (S/D) contact layers, respectively [23]. The total amorphous silicon thickness (t a-Si:H ) is 1700 Å A 0 . ...
We report on the effects of back channel etch depth and etchant chemistry on the electrical characteristics of inverted staggered advanced amorphous silicon thin-film transistors. We found that the optimum amorphous silicon film thickness in the channel is about 800–1100 Å. Three dry etch, HBr + Cl2, C2F6, and CCl2F2 + O2, and one wet etch, KOH, chemistries are used for the back channel etch processing. We established that dry etch can be used for the back channel etch of amorphous silicon transistor without degrading its electrical characteristics.
... Our second approaches (method #2) extract , and separately in a two-step process. A similar method has also been used to extract the threshold voltage of the a-Si:H TFT [27]. The is first defined as the value at which maximum occurs ( V, as illustrated inFig. ...
Bias-temperature-stress (BTS) induced electrical instability of the RF
sputter amorphous In-Ga-Zn-O (a-IGZO) thin-film transistors (TFTs) was
investigated. Both positive and negative BTS were applied and found to
primarily cause a positive and negative voltage shift in transfer (IDS - VGS) characteristics, respectively. The time evolution of bulk-state
density (NBS) and characteristic temperature of the conduction-band-tail-states (TG are extracted. Since both values showed only minor changes after
BTS, the results imply that observed shift in TFT IDS - VGS curves were primarily due to channel charge injection/trapping
rather than defect states creation. We also demonstrated the validity of
using stretch-exponential equation to model both positive and negative BTS
induced threshold voltage shift (ΔVth) of the a-IGZO TFTs. Stress voltage and temperature dependence of ΔVth evolution are described.
... One possible solution is to deposit the TFT active layer in two successive steps-a low-depositionrate film near the a-SiN X :H/a-Si:H interface to achieve a highelectronic-quality a-Si:H film near the electron conduction channel, and a high-deposition-rate film in the back channel to provide an etching buffer. The a-SiN X :H deposition can also be separated into a two-step process-a low-depositionrate film near the high-quality a-Si:H film for optimal electrical performance, and a high-deposition-rate film near the gate metal to reduce the gate leakage [6]. This advanced a-Si:H TFT shows acceptable electrical performance while maintaining a sufficiently high production throughput to be useful in the commercial applications. ...
... The fabrication process for the advanced a-Si:H TFTs has been described elsewhere [6]. All electrical measurements were carried out in a Karl Suss probe station. ...
We fabricated and characterized the advanced amorphous silicon thin-film transistors with a bilayer structure for both the active and gate dielectric films. The electrical field across the gate insulator has a significant influence on the device threshold voltage electrical stability. We show that high thin-film transistor stability can be achieved even under the presence of a high channel current. Its electrical and high-temperature stability improves up to a factor of five when the TFT biasing condition changes from the linear to the saturation region of operation.
Plasma‐enhanced chemical vapor deposition (PECVD) method is widely used for thin‐film deposition of insulating and semiconducting layers in thin‐film transistors (TFT) for active‐matrix liquid‐crystal display (AMLCD) and active‐matrix organic light‐emitting diode (AMOLED) displays. The basic guideline for scaling up PECVD processes generation to generation has been to maintain the same intensive deposition parameters, such as substrate temperature, deposition pressure, and electrode spacing, while somewhat proportionally increasing the extensive deposition parameters such as radio frequency (RF) power and gas flow rate. All modern PECVD chambers are also equipped with in situ dry cleaning capability in the form of a remote plasma source cleaning (RPSC) unit. RPSC technology created a second productivity revolution in mass production PECVD tools due to further improvements in particles and yield performance, as well as enabling a longer lifetime of process chamber components such as diffusers and susceptors.
Flexible thin film transistors (TFTs) have attracted much attention as key components for large-area electronic devices and circuits. A fundamental requirement is low formation temperature of the semiconducting channel for flexible substrate compatibility. Metal oxide materials such as zinc oxide (ZnO), amorphous indium zinc oxide (a-IZO), amorphous zinc tin oxide (a-ZnSnO), aluminium zinc oxide (AZO) and amorphous InGaZnO (a-IGZO) are promising for next-generation microelectronic devices because they exhibit good performance compared to amorphous silicon (a-Si) TFTs and are plastic compatible. Similarly, high-k metal oxide dielectrics offer potential as they offer process compatibility and enhanced device performance, as the gate insulator in TFTs. Therefore, both an individual material and combinational device study is absolutely vital and critical. a-IGZO channel layer TFTs are studied in light of the gate dielectric and source/drain contact metal effects, respectively. In bi-layers dielectric a-IGZO TFTs, a predominant bias-dependant variable charge exists at the dielectric-dielectric interface at high E-fields due to the Maxwell-Wagner instability and alters the behaviour of the TFTs. By adopting ideal MOSFET equations, we account for this anomaly and model this behaviour. The behaviour depends on growth order and thickness of gate dielectric stack. Similarly, in a-IGZO TFTs with different source/drain contact metals, a random bias-dependant variable charge exists at the metal-semiconductor interface due to metal diffusion and oxidation which leads to significant trap generation. Hence a random variable bias-dependant depletion capacitance underneath and in proximity of the contact exists. This effect has been observed for mono-metals and not bi-metal devices. Such behaviour has been modelled using the Pilling-Bedworth theory and variable diode capacitors. Finally, in route to large-area fabrication of devices, an industrial scale high target utilisation sputtering (HiTUS) system has been used for high-k dielectric film depositions. These films were electrically compared to high quality atomic layer deposited films. The results justify this technique’s prolonged use for industrial scaling.
Transparent amorphous oxide semiconductors, especially a-InGaZnO, are the most recent TFT materials of interest for driving active matrix displays. The high level of activity on these devices is because, even though the material is amorphous, it can offer a carrier mobility of 10 cm2/Vs, or more. This is 10–20 times greater than a-Si:H, and the higher mobility is advantageous for driving organic light emitting diode, OLED, displays. Also, due to the amorphous nature of the material, it may have better uniformity than poly-Si, which is the currently preferred TFT technology for commercial, hand-held AMOLED displays. In this chapter, the material and electronic properties of AOS materials are reviewed, paying particular attention to a-InGaZnO TFTs. Other topics include device architecture and fabrication, the DOS and conduction mechanisms within the material, overall device performance, and bias stability issues.
We studied the electrical properties of the room temperature (RT) fabricated amorphous In-Ga-Zn-O thin film transistors (a-IGZO TFTs). The inverted-staggered a-IGZO TFTs fabricated in this work have the following electrical properties: threshold voltage of 4.3V, field-effect mobility of 8.4 cm2V-1s-1, subthreshold swing of 355mV/decade and on/off current ratio over 107. In addition, the a-IGZO thin film shows a very good visible light transparency (closed to 100%). These properties are highly desirable for future optoelectronics.
Current state-of the art image sensor technology has been developed on a flat surface. Recently, due to the unique advantages of a hemispherical image sensor, various methods have been proposed to implement optoelectronic devices on non-planar surfaces. However, more advanced strategy is necessary to realize active-matrix high resolution pixel array on non-planar surfaces. In this dissertation we demonstrate the fabrication of a-Si:H TFTs and passive pixel sensor (PPS) circuits on a curved glass substrate using maskless laser-write lithography (LWL). Further integration of solution-processable organic photodiodes with PPS circuit will realize imagers on a curved surface. First we introduce and discuss the electrical properties and instability of advanced a-Si:H TFT structures for pixel switch applications. Asymmetric electrical properties and the relationship between single and multiple hexagonal TFTs are also established. We used maskless laser-write lithography (LWL) system on a planar surface to demonstrate the feasibility of LWL in fabricating a-Si:H TFTs. We further develop necessary modifications of the LWL system for curved surface application. The fabricated a-Si:H TFTs with a channel length of 10 ??m on a curved surface show acceptable electrical performance as a pixel switch. A high level-to-level alignment accuracy (< ?? 2 ??m) is achieved. The variations of electrical parameters over different curved locations are not significant. Extensive study of the a-Si:H TFTs threshold voltage shift (??Vth) is conducted under prolonged bias-temperature stress condition. Metal interconnect lines over the transition between curved and flat surfaces of a single substrate is demonstrated, which is necessary for placing contact pads on the flat area. Finally we fabricated 128x128 a-Si:H TFT PPS array with 50 ??m pixel pitch on a 4??? silicon wafer to be integrated with the organic photodiode for imager. The pixel circuit consists of fork-shaped a-Si:H TFT (W/L = 40/5) and a storage capacitor (CST, 0.1 pF).
Amorphous silicon based materials, especially a-SiGe : H, have provided a variety of applications in display backplane and sensor materials. The ultimate goal is the development of device architectures that offer improved properties and functionality. In this article, the electrical contact resistivity (ρc) of a-SiGe : H is investigated in terms of the optical energy bandgap modulated by Ge incorporation and the work function of the contact metals. Firstly, the ρc is found to be dependent on the optical bandgap, and this originates from the reduced potential difference between the Fermi level at the metal/a-Si : H interface and the electron mobility edge (Ec), with the decrease in the optical bandgap, which reduces the barrier height. Secondly, the barrier height of the Ti/Cu contact is higher than that of the Mo/Al/Mo contact. In particular, an abundance of Ge atoms is found to have been out-diffused towards the surface and to have formed a mixed interfacial layer, having higher work function than that of the Mo/Al/Mo contact. These results provide evidence that the ρc in a-SiGe : H depends on the work function of the contact layer and is potentially useful for improving device performances.
