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An injection-locked oscillator (ILO) monolithic-microwave
integrated-circuit (MMIC) chain-a cascade of low- and
high-frequency-band ILOs-is proposed for simple and cost-effective
millimeter-wave local oscillators and synthesizers. Primary 5, 20, and
50 GHz-band ILO MMICs are designed and fabricated as an ILO-chain chip
set. Improvements made to the...
Context in source publication
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... a pure output signal for injection into the second-stage ILO. Conventional ILO's use a four-port A-C/D and suffer leakage of the injection signal and its harmonics from the injection signal input port to the output port if an output filter is not used. The circuit scheme and signal flow for the newly designed first-stage ILO MMIC is shown in Fig. 3. The six- port A-C/D, which consists of three active in-phase dividers [a pair of common-gate FET's (CGF's)] connected to one another through their high impedance output ports, effectively solves the problem of leakage [13]. The six-port A-C/D suppresses spurs from the output port because the third in-phase divider prevents signal flow ...
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Citations
... The combination of a VCO with a frequency multiplier can enable the VCO to work at lower frequency which can be designed with better spectral purity [5]- [7]. Injection locking in harmonic oscillators has been applied in frequency multiplication circuits [8]. Injection locking in ring VCO can be used for both injection locked frequency multiplication (ILFM) [9] and injection locked frequency division (ILFD) [10]. ...
This paper proposes an injection locked four stage differential ring voltage controlled oscillator (VCO), in which in-phase and quadrature phase of the reference signal is injected after the first stage, for both frequency multiplication and division. The free running frequency of 4-stage differential VCO is 485MHz. Frequency Multiplication is carried out by injecting a reference frequency of 1.25GHz the corresponding output frequency observed is 1.25GHz. Frequency division is carried out by injecting a reference frequency of 242MHz and a corresponding output frequency of 250MHz is observed.
... In addition to acting as clock receivers, ILOs can be constructed as frequency multipliers [19] or dividers [27], [38], and hence this scheme enables local clock domains to have higher (nf 0 ) or lower clock speed (f 0 /m) than the global clock (f 0 ). Such a global-local clocking scheme with multiple-speed local clocks offers significant improvements over conventional single-speed clocking scheme in terms of power consumption, skew, and jitter. ...
We propose injection-locked clocking (ILC) to combat deteriorating clock skew and jitter, and reduce power consumption in high-performance microprocessors. In the new clocking scheme, injection-locked oscillators are used as local clock receivers. Compared to conventional clocking with buffered trees or grids, ILC can achieve better power efficiency, lower jitter, and much simpler skew compensation thanks to its built-in deskewing capability. Unlike other alternatives, ILC is fully compatible with conventional clock distribution networks. In this paper, a quantitative study based on circuit and microarchitectural-level simulations is performed. Alpha21264 is used as the baseline processor, and is scaled to 0.13 m and 3 GHz. Simulations show 20- and 23-ps jitter reduction, 10.1% and 17% power savings in two ILC configurations. A test chip distributing 5-GHz clock is implemented in a standard 0.18- m CMOS technology and achieved excellent jitter performance and a deskew range up to 80 ps.
... Note that this is different from resonant clocking [8], where all the oscillators are coupled together. Further, ILOs can be constructed as frequency multipliers [12] or dividers [13], [14], and hence this scheme enables local clock domains at higher (Ò ¢ ¼ ) or lower speed ( ¼ Ñ) than the global clock ( ¼ ). Such a global-local clocking scheme with multiple-speed local clocks offers significant improvements over conventional single-speed clocking scheme in terms of power consumption, skew, and jitter. ...
We propose a new GHz clock distribution scheme, injection-locked clocking (ILC). This new scheme uses injection-locked oscillators as the local clock regenerators. It can achieve better power efficiency and jitter performance than conventional buffered trees with the additional benefit of built-in deskewing. A test chip is implemented in a standard 0.18mum digital CMOS technology. It has four divide-by-2 ILOs at the leaves of a 3-section H-tree, generating 5GHz local clocks from the 10GHz input clock with 17% locking range and no phase noise degradation. Measured jitter of generated clocks is lower than that of the input signal. Two local clocks can be differentially deskewed up to 80ps relative to each other. The test chip consumes only 7.3mW excluding test-port buffers
... Therefore, stabilization techniques using pure low-frequency reference signals by way of injection locking and phase-locked loops (PLLs) appear as the viable alternatives to achieve high-purity sources in monolithic forms at mm-wave frequen- cies [11]. The injection locking approach permits simple circuit configuration and has been applied to W-band [9], [11]. However, it results in narrow bandwidth and is susceptible to lock failures when exposed to temperature variations due to the lack of feedback control [11]. ...
A fully integrated V-band phase-locked loop (PLL) MMIC with good phase noise and low-power consumption is developed using 0.15-μm GaAs pHEMTs. For V-band frequency division,a wideband divide-by-3 frequency divider is proposed using cascode FET-based harmonic injection locking. The fourth subharmonic mixer using anti-parallel diode pair is employed as a high-frequency phase detector. In this way, the required frequency of the reference oscillator is lowered to one twelfth of V-band output signal. An RC low-pass filter and DC amplifier are also integrated to effectively suppress the spurious and harmonic signals, and to increase the loop gain. To reduce the circuit interactions and frequency pulling effect, buffer amplifiers are used at the output of VCO and frequency divider. The fabricated V-band PLL MMIC shows the locking range of 840 MHz around 60.1GHz under a very low power dissipation of 370 mW. Good phase noise of -95.5 dBc/Hz is measured at 100 kHz offset. The chip size is as small as 2.35×1.80 mm<sup>2</sup>. To the best of our knowledge, the PLL MMIC of this work is one of the highest frequency monolithic PLLs that integrates all the required elements on a single chip.
... Injection locking of oscillators has been shown to be a useful mechanism to establish a relationship between a free running oscillator and a reference oscillator without requiring a full frequency-synthesizer. Injection locking of harmonic oscillators has been widely used for frequency multiplication [1], for the generation of variable phase shifts [2], and for frequency division [3]. Recently, injection locking of ring oscillators has been used for frequency division [3] and quadrature generation [4]. ...
... We can develop the relationship between d and ∆ as follows. The exponentially decreasing part of v d,i is given by(1) and for v d,in j we obtain: v d,in j (t) = −V ain j,max + (V ain j +V ain j,max ) · e −t+∆ τ . ...
A delay-based time-domain model is used to predict the locking dynamics in injection-locked non-harmonic oscillators, such as ring or relaxation oscillators. The locking dynamics predicted by the model are verified against simulations and measurements of a four-stage ring oscillator circuit built using discrete components
... The authors proposed a monolithic subharmonically injection-locked oscillator (ILO) chain, a cascade of low/high frequency-band ILO's, as a attractive candidate to solve the above problems [4], [5]. The ILO chain is suitable for simple and low-cost millimeter-wave sources because it can achieve much higher multiplication ratios with only one or two chips [6]. ...
... © 1997 IEEE easy to realize ILO chan configuration for a millimeter-wave source. The basic circuit topology as shown in Fig. 1 can be available at any frequencies from the C-band to the millimeterwave frequencies, although some improvements should be to the active combiner/divider for millimeter-wave applications [4]. 1.4 mm . ...
A monolithic subharmonically injection-locked oscillator (ILO)
with wide frequency tuning range using a shunted varactor diode inserted
to the oscillation loop is presented. A 20-GHz-band ILO is fabricated
that achieves the wide injection locking range of more than 700 MHz at
each subharmonic factor up to 32. In addition, the phase-noise
degradation rate of the ILO against the subharmonic factor is close to 6
db/oct. The ILO configuration is extremely suitable for realizing low
cost and low-phase-noise millimeter-wave monolithic microwave integrated
circuit (MMIC) sources
... The mixing operation is realized in SOM using the nonlinearity of the oscillator portion (i.e., a saturated amplifier). A MMIC oscillator circuit is designed similar to the block diagram reported earlier [3]; this new design is composed of the input buffer amplifier, 6-port Active Com/Div, and a voltage controlled oscillator (VCO) . The 19 GHz VCO is constructed using the 14-24 GHz amplifier with an external feedback path including a varactor loaded delay line. ...
Experimental results are presented for an optically fed MMIC based
self-oscillating mixer (SOM) at 19 GHz. A frequency reference, used to
subharmonically synchronize the 19 GHz VCO, and FM data signals are
optically distributed to generate RF signals for Ka-band communication
satellites
Frequency synthesis and conversion are ever-present in RF, microwave and mm-wave circuits, and they are staple building blocks in transceivers (see the familiar block diagram in Fig. 6.1).
This brief describes an efficient way to reduce the quantization noise of delta-sigma fractional-N PLLs by using an injection-locked oscillator (ILO) in the feedback path. For further noise reduction, the use of cascaded ILOs is proposed. Behaving like a type-I high-order PLL, the cascaded ILOs effectively suppress the quantization noise like a high-order phase-domain low-pass filter (PDLPF). We show that the proposed ILO-based PDLPF significantly improves the out-of-band phase noise for wideband fractional-N PLLs as well as the in-band phase noise for fractional-N bang-bang PLLs (BBPLLs). Post-layout simulation results show that a
$\Delta \Sigma $
fractional-N BBPLL with a 3-stage ILO can achieve the in-band noise reduction of 25 dB without having a nested PLL.
Model frameworks, based on Floquet theory, have been shown to produce effective tools for accurately predicting phase‐noise response of single (free‐running) oscillator systems. This method of approach, referred to herein as macro‐modeling, has been discussed in several highly influential papers and now constitutes an established branch of modern circuit theory. The increased application of, for example, injection‐locked oscillators and oscillator arrays in modern communication systems has subsequently exposed the demand for similar rigorous analysis tools aimed at coupled oscillating systems. This paper presents a novel solution in terms of a macro‐model characterizing the phase‐response of synchronized coupled oscillator circuits and systems perturbed by weak noise sources. The framework is generalized and hence applicable to all circuit configurations and coupling topologies generating a synchronized steady‐state. It advances and replaces the phenomenological descriptions currently found in the published literature pertaining to this topic and, as such, represents a significant breakthrough w.r.t. coupled oscillator noise modeling. The proposed model is readily implemented numerically using standard routines. A novel time‐domain model, describing the stochastic phase response of coupled synchronized oscillators perturbed by noise, is proposed. The approach is based on rigorous principles from Floquet theory and the concept of normally‐hyperbolic manifold persistence. The model is verified against solutions produced by a leading commercial simulator program. It is discussed how the model can be applied towards the development of novel numerical algorithms aimed at characterizing coupled oscillator phase‐noise performance.
