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This paper describes the design, realization, and evaluation of a mixed-signal motion estimation processor using the full-search block-matching algorithm. The approach features digital I/O and a low-power, compact analog computational core. The proof-of-concept realization whose architecture incorporates pixel reuse, was fabricated in 0.8-mum CMOS...
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... due to the simplicity in designing a moderate accuracy comparator. A two-stage topology was em- ployed for the 8-bit comparators; a pre-amplification stage fol- lowed by a CMOS dynamic latch. The preamplifier was realized as a simple nMOS input differential pair with diode-connected loads (gain of about 4), and the dynamic latch by the circuit in Fig. 6. The CMOS cross-coupled latch is driven by a high-gain differential pair biased by . The competition between the two input voltages and rep- resenting the current and previous MSE metrics, respectively, is activated by the clock pulse going high. The pMOS switches are used to reset the state of the ...
Citations
... Digital and analog in combination can be complementary. Mixed signal devices can have new functionality, or avoid limitations of analog or digital alone [21]- [23]. Current mixed signal often samples analog, processes by digital, then converts back to analog [22]. ...
Presented is a design of a mixed signal integrator, consisting of a traditional analog integrator (op-amp with capacitor in feedback) augmented with comparators, logic, counter registers, and a precharged capacitor that can be switched into, and out of, the input of the analog integrator. This device integrates with analog, but stores results in analog and digital. Whenever an analog integrator voltage equals or exceeds a threshold voltage, an amount of charge equivalent to the threshold voltage is cleared from the feedback capacitor of the analog integrator, and the counter register is incremented or decremented accordingly. With the threshold voltage representing one in a counting system, these actions convert the integrator contents to ±1. At any instant, the counter register holds the integer portion of the integral, and the analog integrator holds any fractional portion, permitting the integral to be internally stored as a real number. The mixed signal integrator accumulates integral beyond supply rails without op-amp saturation; has analog integrator bandwidth that extends into the limited gain low frequency region; avoids drift due to low pass filter effects and unbalanced input biases; and exhibits no sampled data or discrete system effects. Tests on a PCB prototype verified the design.
This article discusses the harmonic and intermodulation performance of moderate inversion MOSFET transconductors. The bulk of the nMOS transistor is tied to ground, at all levels of inversion, including moderate inversion and the transistor is operating in the saturation region where it behaves qualitatively as a constant current source. The current–voltage characteristic of the transistor is approximated using a Fourier-series model. Using this model, analytical expressions are obtained for amplitudes of the harmonics and intermodulation products resulting from multi-sinusoidal gate-to-source input voltages. The special case of a two equal-amplitude sinusoidal input is considered in detail and the results are compared with previously published results.
In this paper, we propose a Mixed Signal Parallel Multi 1Dimensional Block Matching Algorithm (MSPM-1D-BMA) based motion estimation (ME) processor. In contrast to the typical 2Dimensional full search block matching algorithm (2DFSBMA), the MSPM-1D-BMA based ME processor will greatly reduce the number of data movements in between memories. We employ a voting algorithm in the proposed ME processor to improve the accuracy of motion vector (MV) estimation. We have demonstrated that the MV estimation accuracy achieved by the proposed ME processor is much better than the existing fast block matching algorithms and is close to 2DFSBMA. We also demonstrated that the speed of the proposed ME processor approaches two times as that of the mixed signal 2DFSBMA based ME processor.
In this paper, we propose an expert-system based parallel multi-1-dimensional block matching algorithm (ESPM-1D-BMA) for motion estimation (ME). Instead of the conventional 2D block matching, we employ the parallel multi-1D blocks matching to improve the computing speed. To improve the ME accuracy, we design a knowledge base and inference engine to determine the true motion vector (MV) from the results of parallel multi-1D blocks matching. To speed up the computing speed further, we present a hardware architecture for implementing the ESPM-1D-BMA. We have demonstrated that the MV estimation accuracy achieved by the proposed ESPM-1D-BMA is much better than the comparing fast block matching algorithms and is close to the 2 dimensional full search block matching algorithm (2D-FSBMA). We also demonstrate that the computing speed of the proposed ESPM-1D-BMA is about two times as fast as the mixed-signal 2D-FSBMA (MS-2D-FSBMA).
Two "sweet spots" are analytically identified to enable MOSFET squarer differential transconductors to efficiently operate in moderate inversion. Measurements at low frequencies demonstrate the practicality of using moderate inversion when input signals are limited to about 200 mV<sub>pk-pk</sub>. At the first sweet spot, very low distortion of significantly less than 0.5% total harmonic distortion is possible. For comparison, the sweet spot for the third harmonic is shown for the linear differential transconductor. This brief also discusses the effect of the variations in threshold voltage on the location of the sweet spots, and demonstrates that this sensitivity can be greatly reduced using an appropriate biasing circuit. The proposed approach is of particular interest for low voltage and low current squarer transconductance applications.
